SPI_HOST Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.267m	13.715ms	45	50	90.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	35.972us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	63.683us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	161.126us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	88.498us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	27.806us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	63.683us	20	20	100.00
		spi_host_csr_aliasing	3.000s	88.498us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	17.268us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	29.114us	5	5	100.00
V1		TOTAL			110	115	95.65
V2	performance	spi_host_performance	4.000s	72.534us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.133m	10.194ms	50	50	100.00
		spi_host_error_cmd	3.000s	18.019us	50	50	100.00
		spi_host_event	20.950m	225.393ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.950m	53.405ms	50	50	100.00
V2	speed	spi_host_speed	5.950m	53.405ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.950m	53.405ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	11.350m	22.992ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	559.969us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.950m	53.405ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.950m	53.405ms	50	50	100.00
V2	duplex	spi_host_smoke	10.267m	13.715ms	45	50	90.00
V2	tx_rx_only	spi_host_smoke	10.267m	13.715ms	45	50	90.00
V2	stress_all	spi_host_stress_all	4.850m	20.184ms	50	50	100.00
V2	spien	spi_host_spien	5.133m	13.228ms	50	50	100.00
V2	stall	spi_host_status_stall	10.583m	31.469ms	44	50	88.00
V2	Idlecsbactive	spi_host_idlecsbactive	47.000s	1.821ms	49	50	98.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	25.539us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	91.477us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	403.858us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	403.858us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	35.972us	5	5	100.00
		spi_host_csr_rw	3.000s	63.683us	20	20	100.00
		spi_host_csr_aliasing	3.000s	88.498us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	33.525us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	35.972us	5	5	100.00
		spi_host_csr_rw	3.000s	63.683us	20	20	100.00
		spi_host_csr_aliasing	3.000s	88.498us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	33.525us	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	81.914us	20	20	100.00
		spi_host_sec_cm	3.000s	123.984us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	81.914us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			818	830	98.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	13	81.25
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.90	96.72	93.10	98.48	96.73	95.70	100.00	98.60	90.46

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 6 failures:
- Test spi_host_smoke has 4 failures.
  - 1.spi_host_smoke.101454857560333290884086337050568141609220064115817362592102515743184084058442
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 76983031602 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x805ec094) == 0x0
  UVM_INFO @ 76983031602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.spi_host_smoke.45324650373990774604515659072962043792286106551674757561086382029862500024110
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 98337146535 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x705e5454) == 0x0
  UVM_INFO @ 98337146535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test spi_host_idlecsbactive has 1 failures.
  - 42.spi_host_idlecsbactive.111411945316783371981774557396197204816087767472609861146510529342415268295549
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10038749481 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6ee78354) == 0x0
  UVM_INFO @ 10038749481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 48.spi_host_status_stall.87416800906266637426553545412160979895106663015902473393497047781653316042303
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 63387410574 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x54b9014) == 0x0
  UVM_INFO @ 63387410574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 3 failures:
- Test spi_host_status_stall has 3 failures.
  - 13.spi_host_status_stall.89812523789995264623037663550004758952529341468564593743529681775555400096213
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 11847408762 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe5a9fcd4) == 0x1
  UVM_INFO @ 11847408762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.spi_host_status_stall.39279212807848556175420039335409618846441642163307600582452245449311734102676
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 33430301748 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x864661d4) == 0x1
  UVM_INFO @ 33430301748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
- Test spi_host_status_stall has 2 failures.
  - 24.spi_host_status_stall.38670645583825310773009075199372349241288478557101055622060790675301707721081
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 14676114276 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x49891994) == 0x1
  UVM_INFO @ 14676114276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.spi_host_status_stall.5604647718172196695371186394420326479399270933003044563755597422658954870848
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 31469448780 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x29c4c394) == 0x1
  UVM_INFO @ 31469448780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 30.spi_host_smoke.89015196151903875592987622798254527050819678947358636373325864687711491896356
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 186168232853 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6224c614) == 0x0
  UVM_INFO @ 186168232853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `2723ca659d`