SPI_HOST Simulation Results

Thursday April 11 2024 19:07:25 UTC

GitHub Revision: 1f410ef5dc

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77676901304510083363507443373754332549719316834151559528665885252978172929472

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 9.583m 87.600ms 48 50 96.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 86.920us 5 5 100.00
V1 csr_rw spi_host_csr_rw 4.000s 23.792us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 4.000s 1.694ms 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 173.922us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 4.000s 96.241us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 4.000s 23.792us 20 20 100.00
spi_host_csr_aliasing 3.000s 173.922us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 23.146us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 62.955us 5 5 100.00
V1 TOTAL 113 115 98.26
V2 performance spi_host_performance 8.000s 96.434us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.283m 8.417ms 49 50 98.00
spi_host_error_cmd 8.000s 60.944us 50 50 100.00
spi_host_event 22.233m 64.380ms 50 50 100.00
V2 clock_rate spi_host_speed 4.467m 20.832ms 50 50 100.00
V2 speed spi_host_speed 4.467m 20.832ms 50 50 100.00
V2 chip_select_timing spi_host_speed 4.467m 20.832ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 12.467m 28.270ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 9.000s 506.772us 50 50 100.00
V2 cpol_cpha spi_host_speed 4.467m 20.832ms 50 50 100.00
V2 full_cycle spi_host_speed 4.467m 20.832ms 50 50 100.00
V2 duplex spi_host_smoke 9.583m 87.600ms 48 50 96.00
V2 tx_rx_only spi_host_smoke 9.583m 87.600ms 48 50 96.00
V2 stress_all spi_host_stress_all 4.267m 5.684ms 49 50 98.00
V2 spien spi_host_spien 7.733m 63.803ms 49 50 98.00
V2 stall spi_host_status_stall 8.817m 50.572ms 47 50 94.00
V2 Idlecsbactive spi_host_idlecsbactive 44.000s 6.401ms 48 50 96.00
V2 data_fifo_status data_fifo_status 0 0 --
V2 alert_test spi_host_alert_test 12.000s 19.865us 50 50 100.00
V2 intr_test spi_host_intr_test 5.000s 17.510us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 33.132us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 33.132us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 86.920us 5 5 100.00
spi_host_csr_rw 4.000s 23.792us 20 20 100.00
spi_host_csr_aliasing 3.000s 173.922us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 70.116us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 86.920us 5 5 100.00
spi_host_csr_rw 4.000s 23.792us 20 20 100.00
spi_host_csr_aliasing 3.000s 173.922us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 70.116us 20 20 100.00
V2 TOTAL 682 690 98.84
V2S tl_intg_err spi_host_tl_intg_err 4.000s 85.728us 20 20 100.00
spi_host_sec_cm 2.000s 245.615us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 85.728us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 820 830 98.80

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 15 10 62.50
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.88 96.67 93.00 98.48 96.64 95.70 100.00 98.60 90.87

Failure Buckets

Past Results