1f410ef5dc
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_host_smoke | 9.583m | 87.600ms | 48 | 50 | 96.00 |
V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 86.920us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_host_csr_rw | 4.000s | 23.792us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_host_csr_bit_bash | 4.000s | 1.694ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 173.922us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 96.241us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 4.000s | 23.792us | 20 | 20 | 100.00 |
spi_host_csr_aliasing | 3.000s | 173.922us | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_host_mem_walk | 3.000s | 23.146us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 62.955us | 5 | 5 | 100.00 |
V1 | TOTAL | 113 | 115 | 98.26 | |||
V2 | performance | spi_host_performance | 8.000s | 96.434us | 50 | 50 | 100.00 |
V2 | error_event_intr | spi_host_overflow_underflow | 3.283m | 8.417ms | 49 | 50 | 98.00 |
spi_host_error_cmd | 8.000s | 60.944us | 50 | 50 | 100.00 | ||
spi_host_event | 22.233m | 64.380ms | 50 | 50 | 100.00 | ||
V2 | clock_rate | spi_host_speed | 4.467m | 20.832ms | 50 | 50 | 100.00 |
V2 | speed | spi_host_speed | 4.467m | 20.832ms | 50 | 50 | 100.00 |
V2 | chip_select_timing | spi_host_speed | 4.467m | 20.832ms | 50 | 50 | 100.00 |
V2 | sw_reset | spi_host_sw_reset | 12.467m | 28.270ms | 50 | 50 | 100.00 |
V2 | passthrough_mode | spi_host_passthrough_mode | 9.000s | 506.772us | 50 | 50 | 100.00 |
V2 | cpol_cpha | spi_host_speed | 4.467m | 20.832ms | 50 | 50 | 100.00 |
V2 | full_cycle | spi_host_speed | 4.467m | 20.832ms | 50 | 50 | 100.00 |
V2 | duplex | spi_host_smoke | 9.583m | 87.600ms | 48 | 50 | 96.00 |
V2 | tx_rx_only | spi_host_smoke | 9.583m | 87.600ms | 48 | 50 | 96.00 |
V2 | stress_all | spi_host_stress_all | 4.267m | 5.684ms | 49 | 50 | 98.00 |
V2 | spien | spi_host_spien | 7.733m | 63.803ms | 49 | 50 | 98.00 |
V2 | stall | spi_host_status_stall | 8.817m | 50.572ms | 47 | 50 | 94.00 |
V2 | Idlecsbactive | spi_host_idlecsbactive | 44.000s | 6.401ms | 48 | 50 | 96.00 |
V2 | data_fifo_status | data_fifo_status | 0 | 0 | -- | ||
V2 | alert_test | spi_host_alert_test | 12.000s | 19.865us | 50 | 50 | 100.00 |
V2 | intr_test | spi_host_intr_test | 5.000s | 17.510us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 33.132us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 33.132us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 86.920us | 5 | 5 | 100.00 |
spi_host_csr_rw | 4.000s | 23.792us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 3.000s | 173.922us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 3.000s | 70.116us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 86.920us | 5 | 5 | 100.00 |
spi_host_csr_rw | 4.000s | 23.792us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 3.000s | 173.922us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 3.000s | 70.116us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 682 | 690 | 98.84 | |||
V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 85.728us | 20 | 20 | 100.00 |
spi_host_sec_cm | 2.000s | 245.615us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 85.728us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | winbond | winbond | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 820 | 830 | 98.80 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 7 | 87.50 |
V2 | 16 | 15 | 10 | 62.50 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 2 | 0 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
96.88 | 96.67 | 93.00 | 98.48 | 96.64 | 95.70 | 100.00 | 98.60 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 7 failures:
Test spi_host_status_stall has 3 failures.
9.spi_host_status_stall.93510022974155744459500104491192893686952520354000744264368960983470976364646
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log
UVM_FATAL @ 43650254603 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1b118c54) == 0x0
UVM_INFO @ 43650254603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_status_stall.90253326331725141318445370947922518784797847901490715584996447516971992354809
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
UVM_FATAL @ 146730165656 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5ed7af94) == 0x0
UVM_INFO @ 146730165656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_idlecsbactive has 2 failures.
13.spi_host_idlecsbactive.69415613313869854904275052305227157120915860961978087403899616935285660389954
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10072416155 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8b62fb94) == 0x0
UVM_INFO @ 10072416155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.spi_host_idlecsbactive.28404501768985642801441817811052615566598686901418242936384221256079526728503
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10041949369 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe5568d4) == 0x0
UVM_INFO @ 10041949369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_overflow_underflow has 1 failures.
23.spi_host_overflow_underflow.14290159707666805812902477480434833230816007704215191917799052542630034001738
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 33836588860 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x10225a94) == 0x0
UVM_INFO @ 33836588860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
34.spi_host_stress_all.12690394407326567530794783149425194808676652111585943103612092911896453354283
Line 299, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_stress_all/latest/run.log
UVM_FATAL @ 24191703864 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb31c76d4) == 0x0
UVM_INFO @ 24191703864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 2 failures:
21.spi_host_smoke.109743150985977591376088186750125709877378375494877226774853353716338911582687
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_smoke/latest/run.log
UVM_FATAL @ 99272197567 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x665f9e14) == 0x0
UVM_INFO @ 99272197567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_host_smoke.82173259673531076684811917155805783717100299489118129228499501140175817390638
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_smoke/latest/run.log
UVM_FATAL @ 129801443558 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xaf005b94) == 0x0
UVM_INFO @ 129801443558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == *
has 1 failures:
6.spi_host_spien.76342238423972590430855413082113489556183861484206207085905677107696702196283
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_spien/latest/run.log
UVM_FATAL @ 59093809545 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x906b0414) == 0x1
UVM_INFO @ 59093809545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---