SPI_HOST Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: `9f4903e77a`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.950m	53.398ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	19.807us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	40.931us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	198.989us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	24.453us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	39.388us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	40.931us	20	20	100.00
		spi_host_csr_aliasing	3.000s	24.453us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	105.525us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	28.084us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	4.000s	391.188us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.733m	61.866ms	47	50	94.00
		spi_host_error_cmd	3.000s	50.022us	50	50	100.00
		spi_host_event	17.900m	71.889ms	50	50	100.00
V2	clock_rate	spi_host_speed	3.350m	4.348ms	50	50	100.00
V2	speed	spi_host_speed	3.350m	4.348ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	3.350m	4.348ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	10.683m	39.932ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	291.917us	50	50	100.00
V2	cpol_cpha	spi_host_speed	3.350m	4.348ms	50	50	100.00
V2	full_cycle	spi_host_speed	3.350m	4.348ms	50	50	100.00
V2	duplex	spi_host_smoke	10.950m	53.398ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	10.950m	53.398ms	48	50	96.00
V2	stress_all	spi_host_stress_all	3.317m	6.011ms	48	50	96.00
V2	spien	spi_host_spien	7.233m	33.457ms	50	50	100.00
V2	stall	spi_host_status_stall	10.800m	57.137ms	46	50	92.00
V2	Idlecsbactive	spi_host_idlecsbactive	41.000s	15.951ms	50	50	100.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	17.530us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	36.244us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	495.634us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	495.634us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	19.807us	5	5	100.00
		spi_host_csr_rw	3.000s	40.931us	20	20	100.00
		spi_host_csr_aliasing	3.000s	24.453us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	41.883us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	19.807us	5	5	100.00
		spi_host_csr_rw	3.000s	40.931us	20	20	100.00
		spi_host_csr_aliasing	3.000s	24.453us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	41.883us	20	20	100.00
V2		TOTAL			681	690	98.70
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	286.524us	20	20	100.00
		spi_host_sec_cm	2.000s	225.438us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	286.524us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			819	830	98.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	12	75.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.90	96.67	93.00	98.48	96.82	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 9 failures:
- Test spi_host_status_stall has 3 failures.
  - 0.spi_host_status_stall.39323593283961799167944205034311292498504663258643751783537169314844252314727
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 39877183774 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbadcae54) == 0x0
  UVM_INFO @ 39877183774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.spi_host_status_stall.95749478751880362824834854140085558254630642954468323010887799506390883715581
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 135283305591 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd1d540d4) == 0x0
  UVM_INFO @ 135283305591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_overflow_underflow has 3 failures.
  - 4.spi_host_overflow_underflow.77129263728476068665697135897531956148671076585602812285958957922675773505520
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 40727318197 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x89b49d94) == 0x0
  UVM_INFO @ 40727318197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.spi_host_overflow_underflow.73840063201764283448102395162179015586631625908622823827147619486618476138556
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 43310849010 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbe1cf94) == 0x0
  UVM_INFO @ 43310849010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_smoke has 2 failures.
  - 17.spi_host_smoke.66371424560308420796299466092277211747664510998248253526241008463410515097418
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 105353734862 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4a3d3114) == 0x0
  UVM_INFO @ 105353734862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.spi_host_smoke.4452536451148118309910663345927289614118083700319085695587444393486042919932
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 192215294915 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb2d10494) == 0x0
  UVM_INFO @ 192215294915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 1 failures.
  - 38.spi_host_stress_all.107059884391060535685663173226733528800826732715412518206598463186538846375559
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 26960477110 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3f222c94) == 0x0
  UVM_INFO @ 26960477110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 19.spi_host_stress_all.27540206796863743147499868295865634787363893981538052258650598718005615889042
    Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 19314707455 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x82fb9d4) == 0x0
  UVM_INFO @ 19314707455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 42.spi_host_status_stall.40825444492653622132667708759157488422391795278940950338645859375816114256239
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 42630562086 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc487994) == 0x1
  UVM_INFO @ 42630562086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9f4903e77a`