SPI_HOST Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: `1c75f24e99`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.583m	147.324ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	22.271us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	17.122us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	880.135us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	49.700us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	33.513us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	17.122us	20	20	100.00
		spi_host_csr_aliasing	3.000s	49.700us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	15.612us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	20.968us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	4.000s	85.468us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.783m	3.528ms	50	50	100.00
		spi_host_error_cmd	8.000s	26.044us	50	50	100.00
		spi_host_event	27.533m	153.413ms	50	50	100.00
V2	clock_rate	spi_host_speed	4.733m	40.217ms	50	50	100.00
V2	speed	spi_host_speed	4.733m	40.217ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	4.733m	40.217ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	5.700m	34.117ms	48	50	96.00
V2	passthrough_mode	spi_host_passthrough_mode	8.000s	202.461us	50	50	100.00
V2	cpol_cpha	spi_host_speed	4.733m	40.217ms	50	50	100.00
V2	full_cycle	spi_host_speed	4.733m	40.217ms	50	50	100.00
V2	duplex	spi_host_smoke	9.583m	147.324ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	9.583m	147.324ms	48	50	96.00
V2	stress_all	spi_host_stress_all	4.717m	17.729ms	50	50	100.00
V2	spien	spi_host_spien	7.567m	59.088ms	50	50	100.00
V2	stall	spi_host_status_stall	9.783m	50.571ms	46	50	92.00
V2	Idlecsbactive	spi_host_idlecsbactive	39.000s	1.572ms	50	50	100.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	7.000s	17.326us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	53.356us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	353.405us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	353.405us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	22.271us	5	5	100.00
		spi_host_csr_rw	3.000s	17.122us	20	20	100.00
		spi_host_csr_aliasing	3.000s	49.700us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	45.539us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	22.271us	5	5	100.00
		spi_host_csr_rw	3.000s	17.122us	20	20	100.00
		spi_host_csr_aliasing	3.000s	49.700us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	45.539us	20	20	100.00
V2		TOTAL			684	690	99.13
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	58.189us	20	20	100.00
		spi_host_sec_cm	7.000s	62.463us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	58.189us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			822	830	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	13	81.25
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.88	96.68	93.00	98.48	96.64	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
- Test spi_host_status_stall has 3 failures.
  - 12.spi_host_status_stall.68878893656152160981356097227321078856917727050687379926695305704668920149500
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 97961033708 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x882719d4) == 0x0
  UVM_INFO @ 97961033708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.spi_host_status_stall.70618112482636666170326194156661397471390431717294128948013139417602681528432
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 53069601009 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x250e4254) == 0x0
  UVM_INFO @ 53069601009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_smoke has 1 failures.
  - 30.spi_host_smoke.105010191952098411949308164378340861034383945350699002109823020533886250985649
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 147323753708 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb2799d14) == 0x0
  UVM_INFO @ 147323753708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
- Test spi_host_status_stall has 1 failures.
  - 1.spi_host_status_stall.34116985563819172573800648525640773237006986681865057186624882577482790090774
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 113236491038 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa94f28d4) == 0x0
  UVM_INFO @ 113236491038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 1 failures.
  - 27.spi_host_smoke.39290647047039588250477304287200715479608082890650251382802012159025045875019
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 122577098458 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7184ba94) == 0x0
  UVM_INFO @ 122577098458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:
- Test spi_host_sw_reset has 2 failures.
  - 39.spi_host_sw_reset.115128582091682868649578746963419473747776243900206494647469001644272970510332
    Line 324, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 14788578328 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf1fd9d14) == 0x0
  UVM_INFO @ 14788578328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.spi_host_sw_reset.83503570586009622321428250440071477349344221649460622356053168157874904658996
    Line 366, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 10050951253 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb66fe354) == 0x0
  UVM_INFO @ 10050951253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `1c75f24e99`