SPI_HOST Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.283m	116.324ms	47	50	94.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	32.621us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	7.000s	17.558us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	165.303us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	47.433us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	82.508us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	7.000s	17.558us	20	20	100.00
		spi_host_csr_aliasing	3.000s	47.433us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	22.523us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	41.976us	5	5	100.00
V1		TOTAL			112	115	97.39
V2	performance	spi_host_performance	13.000s	35.986us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.483m	3.060ms	49	50	98.00
		spi_host_error_cmd	7.000s	52.809us	50	50	100.00
		spi_host_event	22.217m	66.346ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.200m	6.974ms	50	50	100.00
V2	speed	spi_host_speed	5.200m	6.974ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.200m	6.974ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	5.133m	10.810ms	49	50	98.00
V2	passthrough_mode	spi_host_passthrough_mode	8.000s	1.147ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.200m	6.974ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.200m	6.974ms	50	50	100.00
V2	duplex	spi_host_smoke	10.283m	116.324ms	47	50	94.00
V2	tx_rx_only	spi_host_smoke	10.283m	116.324ms	47	50	94.00
V2	stress_all	spi_host_stress_all	3.433m	10.004ms	49	50	98.00
V2	spien	spi_host_spien	7.133m	9.297ms	50	50	100.00
V2	stall	spi_host_status_stall	9.650m	41.002ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	37.000s	2.769ms	49	50	98.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	12.000s	18.050us	50	50	100.00
V2	intr_test	spi_host_intr_test	17.000s	44.864us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	10.000s	72.035us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	10.000s	72.035us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	32.621us	5	5	100.00
		spi_host_csr_rw	7.000s	17.558us	20	20	100.00
		spi_host_csr_aliasing	3.000s	47.433us	5	5	100.00
		spi_host_same_csr_outstanding	8.000s	29.542us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	32.621us	5	5	100.00
		spi_host_csr_rw	7.000s	17.558us	20	20	100.00
		spi_host_csr_aliasing	3.000s	47.433us	5	5	100.00
		spi_host_same_csr_outstanding	8.000s	29.542us	20	20	100.00
V2		TOTAL			684	690	99.13
V2S	tl_intg_err	spi_host_tl_intg_err	8.000s	763.887us	20	20	100.00
		spi_host_sec_cm	3.000s	69.298us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	8.000s	763.887us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			821	830	98.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	10	62.50
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.88	96.68	93.00	98.48	96.73	95.70	100.00	98.60	90.46

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
- Test spi_host_smoke has 2 failures.
  - 25.spi_host_smoke.105373282131444930200869919372889015304717661278156687270904049948824495842118
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 84063660958 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbbd28e94) == 0x0
  UVM_INFO @ 84063660958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.spi_host_smoke.113966219449635199410237893791044304465174442978901107640380168744114706737706
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 121240815769 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc7e39c94) == 0x0
  UVM_INFO @ 121240815769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 29.spi_host_status_stall.53245156248866460850926786289344572023384874382680748159471429536423784095716
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 151332039738 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x55b4de54) == 0x0
  UVM_INFO @ 151332039738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_idlecsbactive has 1 failures.
  - 32.spi_host_idlecsbactive.15606838146244424123220204679779610894483072489892674436292023341131586756429
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10088678523 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x69aa12d4) == 0x0
  UVM_INFO @ 10088678523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
- Test spi_host_status_stall has 1 failures.
  - 1.spi_host_status_stall.20878328100348649788321954862900476580138390509094517492145335207992237852111
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 128065469169 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc7223d54) == 0x0
  UVM_INFO @ 128065469169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_overflow_underflow has 1 failures.
  - 48.spi_host_overflow_underflow.55839327619502812579061279105577112111036200645073630929722014091309615557388
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 40156825901 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xef5e8fd4) == 0x0
  UVM_INFO @ 40156825901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:
- Test spi_host_stress_all has 1 failures.
  - 22.spi_host_stress_all.69934452488661391859264808365830421858310149899235858624376408880024946085457
    Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10003860944 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf05a3714) == 0x0
  UVM_INFO @ 10003860944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_sw_reset has 1 failures.
  - 44.spi_host_sw_reset.41074667308073674009666469905771705515222927566683817655930410769567988158058
    Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 15240195506 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x904f4214) == 0x0
  UVM_INFO @ 15240195506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 13.spi_host_smoke.44387156963917654138898304756403365558992725178331083671041245071465846093876
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d3942ca074`