SPI_HOST Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: `4fd94db59a`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.350m	13.369ms	46	50	92.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	31.938us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	17.679us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	857.000us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	59.039us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	34.799us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	17.679us	20	20	100.00
		spi_host_csr_aliasing	2.000s	59.039us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	26.481us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	49.588us	5	5	100.00
V1		TOTAL			111	115	96.52
V2	performance	spi_host_performance	3.000s	139.495us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.467m	9.328ms	50	50	100.00
		spi_host_error_cmd	3.000s	18.749us	50	50	100.00
		spi_host_event	23.800m	214.960ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.017m	33.357ms	50	50	100.00
V2	speed	spi_host_speed	6.017m	33.357ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.017m	33.357ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	6.317m	14.282ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	1.544ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.017m	33.357ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.017m	33.357ms	50	50	100.00
V2	duplex	spi_host_smoke	10.350m	13.369ms	46	50	92.00
V2	tx_rx_only	spi_host_smoke	10.350m	13.369ms	46	50	92.00
V2	stress_all	spi_host_stress_all	5.633m	21.691ms	48	50	96.00
V2	spien	spi_host_spien	6.200m	8.037ms	50	50	100.00
V2	stall	spi_host_status_stall	8.667m	12.229ms	46	50	92.00
V2	Idlecsbactive	spi_host_idlecsbactive	42.000s	1.762ms	49	50	98.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	16.569us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	18.846us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	96.905us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	96.905us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	31.938us	5	5	100.00
		spi_host_csr_rw	3.000s	17.679us	20	20	100.00
		spi_host_csr_aliasing	2.000s	59.039us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	22.609us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	31.938us	5	5	100.00
		spi_host_csr_rw	3.000s	17.679us	20	20	100.00
		spi_host_csr_aliasing	2.000s	59.039us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	22.609us	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	175.407us	20	20	100.00
		spi_host_sec_cm	3.000s	43.052us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	175.407us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			819	830	98.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	12	75.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.49	96.19	92.01	98.06	96.81	95.70	100.00	98.60	90.46

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 7 failures:
- Test spi_host_idlecsbactive has 1 failures.
  - 2.spi_host_idlecsbactive.66168301549632749791386526409446624564059971098975592949406198831988917895216
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10063350024 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5bc592d4) == 0x0
  UVM_INFO @ 10063350024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 3 failures.
  - 4.spi_host_status_stall.26034332064602063637602323718375608582249519685122441597220529291298586488359
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 41871683802 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf49725d4) == 0x0
  UVM_INFO @ 41871683802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.spi_host_status_stall.88588207125439531055166271343143843917327896748788242898955708686078300867189
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 134615233068 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcbe3af94) == 0x0
  UVM_INFO @ 134615233068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_smoke has 2 failures.
  - 31.spi_host_smoke.88267239737970766311908268700594267715817357498271467988718032812073594898453
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 153839289728 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x962ef094) == 0x0
  UVM_INFO @ 153839289728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.spi_host_smoke.107279326084787801509457860059360261820471863314458952527499983072346713487269
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 70719809681 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe755a854) == 0x0
  UVM_INFO @ 70719809681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 1 failures.
  - 49.spi_host_stress_all.67365738021712414044107458286093375533844491225369627311718296981861586882087
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 19591748807 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb3d56614) == 0x0
  UVM_INFO @ 19591748807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
- Test spi_host_smoke has 2 failures.
  - 18.spi_host_smoke.14932097214461523852059222010856345205050843747973938682265435664721198567039
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 73031727912 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6acd1c14) == 0x0
  UVM_INFO @ 73031727912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.spi_host_smoke.3998498754744734948098831275400338503004734352988727313621325069515567929114
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 133777756882 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xfe15c294) == 0x0
  UVM_INFO @ 133777756882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 12.spi_host_status_stall.47105917764160676393188980630979827780389474635946840117232674695456455183599
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 23515407409 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2392a794) == 0x1
  UVM_INFO @ 23515407409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 47.spi_host_stress_all.100378791266757465990089322726813958673926181558485701418669805552964943971487
    Line 315, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10036070187 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa053b54) == 0x0
  UVM_INFO @ 10036070187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4fd94db59a`