SPI_HOST Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	12.117m	195.361ms	47	50	94.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	39.173us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	7.000s	18.183us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	604.846us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	7.000s	72.643us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	43.271us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	7.000s	18.183us	20	20	100.00
		spi_host_csr_aliasing	7.000s	72.643us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	16.278us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	7.000s	24.085us	5	5	100.00
V1		TOTAL			112	115	97.39
V2	performance	spi_host_performance	4.000s	107.683us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.700m	3.648ms	50	50	100.00
		spi_host_error_cmd	4.000s	32.049us	50	50	100.00
		spi_host_event	21.333m	59.382ms	50	50	100.00
V2	clock_rate	spi_host_speed	4.767m	22.466ms	50	50	100.00
V2	speed	spi_host_speed	4.767m	22.466ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	4.767m	22.466ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	8.683m	18.478ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	1.185ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	4.767m	22.466ms	50	50	100.00
V2	full_cycle	spi_host_speed	4.767m	22.466ms	50	50	100.00
V2	duplex	spi_host_smoke	12.117m	195.361ms	47	50	94.00
V2	tx_rx_only	spi_host_smoke	12.117m	195.361ms	47	50	94.00
V2	stress_all	spi_host_stress_all	3.733m	8.215ms	48	50	96.00
V2	spien	spi_host_spien	6.483m	15.440ms	49	50	98.00
V2	stall	spi_host_status_stall	9.967m	26.278ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	49.000s	1.771ms	50	50	100.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	142.933us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	77.764us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	108.097us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	108.097us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	39.173us	5	5	100.00
		spi_host_csr_rw	7.000s	18.183us	20	20	100.00
		spi_host_csr_aliasing	7.000s	72.643us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	34.029us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	39.173us	5	5	100.00
		spi_host_csr_rw	7.000s	18.183us	20	20	100.00
		spi_host_csr_aliasing	7.000s	72.643us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	34.029us	20	20	100.00
V2		TOTAL			684	690	99.13
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	94.162us	20	20	100.00
		spi_host_sec_cm	3.000s	41.548us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	94.162us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			821	830	98.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	12	75.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.50	96.23	92.11	98.06	96.72	95.70	100.00	98.60	90.46

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:
- Test spi_host_smoke has 3 failures.
  - 3.spi_host_smoke.12558512711208960346051171231772831805970200533274332162879883402416263271328
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 78695580323 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3f8b1914) == 0x0
  UVM_INFO @ 78695580323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.spi_host_smoke.87145547749459027951880600248569310471614625779216835843664800674439405028568
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 195360617501 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xdf626cd4) == 0x0
  UVM_INFO @ 195360617501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_stress_all has 1 failures.
  - 11.spi_host_stress_all.40010988973726734566345448226334563705233210789085024677624570708715497832548
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 26824792153 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x94f6e554) == 0x0
  UVM_INFO @ 26824792153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 39.spi_host_status_stall.90674541091463047112926557752466230769825365329387180467373540401635206525275
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 102763400158 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6c13dc14) == 0x0
  UVM_INFO @ 102763400158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
- Test spi_host_status_stall has 1 failures.
  - 9.spi_host_status_stall.38560999192201296253384872753100606452800745871706484415493885560717480926023
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 108295591393 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x35b690d4) == 0x0
  UVM_INFO @ 108295591393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 1 failures.
  - 45.spi_host_stress_all.53756782015832961869341717892462780184957665018139665773011236053767141632230
    Line 299, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 15608052910 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe9e9c614) == 0x0
  UVM_INFO @ 15608052910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 0.spi_host_status_stall.87959106801328460076007213767413314184504594726869384050901696159493543555227
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 19628418809 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd8aece14) == 0x1
  UVM_INFO @ 19628418809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 46.spi_host_spien.4623905647206441973778544151999406553626551591089873244706195996340719714265
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 10016583979 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x18419314) == 0x0
  UVM_INFO @ 10016583979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `41bc3e0c7f`