SPI_HOST Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 11.467m 52.416ms 49 50 98.00
V1 csr_hw_reset spi_host_csr_hw_reset 4.000s 65.179us 5 5 100.00
V1 csr_rw spi_host_csr_rw 12.000s 48.866us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 8.000s 127.947us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 21.212us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 17.000s 26.092us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 12.000s 48.866us 20 20 100.00
spi_host_csr_aliasing 3.000s 21.212us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 15.858us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 18.910us 5 5 100.00
V1 TOTAL 114 115 99.13
V2 performance spi_host_performance 4.000s 75.253us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.700m 6.915ms 50 50 100.00
spi_host_error_cmd 3.000s 20.452us 50 50 100.00
spi_host_event 19.700m 30.245ms 50 50 100.00
V2 clock_rate spi_host_speed 4.417m 5.415ms 50 50 100.00
V2 speed spi_host_speed 4.417m 5.415ms 50 50 100.00
V2 chip_select_timing spi_host_speed 4.417m 5.415ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 7.183m 27.592ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 278.010us 50 50 100.00
V2 cpol_cpha spi_host_speed 4.417m 5.415ms 50 50 100.00
V2 full_cycle spi_host_speed 4.417m 5.415ms 50 50 100.00
V2 duplex spi_host_smoke 11.467m 52.416ms 49 50 98.00
V2 tx_rx_only spi_host_smoke 11.467m 52.416ms 49 50 98.00
V2 stress_all spi_host_stress_all 4.333m 28.962ms 50 50 100.00
V2 spien spi_host_spien 6.317m 34.558ms 50 50 100.00
V2 stall spi_host_status_stall 9.900m 13.993ms 47 50 94.00
V2 Idlecsbactive spi_host_idlecsbactive 45.000s 6.599ms 50 50 100.00
V2 data_fifo_status data_fifo_status 0 0 --
V2 alert_test spi_host_alert_test 3.000s 15.848us 50 50 100.00
V2 intr_test spi_host_intr_test 7.000s 77.282us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 9.000s 36.190us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 9.000s 36.190us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 4.000s 65.179us 5 5 100.00
spi_host_csr_rw 12.000s 48.866us 20 20 100.00
spi_host_csr_aliasing 3.000s 21.212us 5 5 100.00
spi_host_same_csr_outstanding 8.000s 70.531us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 4.000s 65.179us 5 5 100.00
spi_host_csr_rw 12.000s 48.866us 20 20 100.00
spi_host_csr_aliasing 3.000s 21.212us 5 5 100.00
spi_host_same_csr_outstanding 8.000s 70.531us 20 20 100.00
V2 TOTAL 687 690 99.57
V2S tl_intg_err spi_host_tl_intg_err 12.000s 238.172us 20 20 100.00
spi_host_sec_cm 3.000s 359.002us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 12.000s 238.172us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 826 830 99.52

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 15 14 87.50
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.50 96.19 92.01 98.06 96.81 95.70 100.00 98.60 90.87

Failure Buckets

Past Results