SPI_HOST Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.883m 55.657ms 49 50 98.00
V1 csr_hw_reset spi_host_csr_hw_reset 14.000s 25.201us 5 5 100.00
V1 csr_rw spi_host_csr_rw 13.000s 66.234us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 11.000s 650.075us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 5.000s 54.251us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 11.000s 108.442us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 13.000s 66.234us 20 20 100.00
spi_host_csr_aliasing 5.000s 54.251us 5 5 100.00
V1 mem_walk spi_host_mem_walk 9.000s 34.834us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 5.000s 154.559us 5 5 100.00
V1 TOTAL 114 115 99.13
V2 performance spi_host_performance 13.000s 32.086us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.233m 7.551ms 50 50 100.00
spi_host_error_cmd 16.000s 90.755us 50 50 100.00
spi_host_event 15.683m 87.821ms 50 50 100.00
V2 clock_rate spi_host_speed 4.967m 6.794ms 50 50 100.00
V2 speed spi_host_speed 4.967m 6.794ms 50 50 100.00
V2 chip_select_timing spi_host_speed 4.967m 6.794ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 5.033m 21.303ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 18.000s 224.664us 50 50 100.00
V2 cpol_cpha spi_host_speed 4.967m 6.794ms 50 50 100.00
V2 full_cycle spi_host_speed 4.967m 6.794ms 50 50 100.00
V2 duplex spi_host_smoke 10.883m 55.657ms 49 50 98.00
V2 tx_rx_only spi_host_smoke 10.883m 55.657ms 49 50 98.00
V2 stress_all spi_host_stress_all 4.583m 43.393ms 49 50 98.00
V2 spien spi_host_spien 6.217m 50.514ms 50 50 100.00
V2 stall spi_host_status_stall 9.317m 13.959ms 47 50 94.00
V2 Idlecsbactive spi_host_idlecsbactive 47.000s 1.636ms 50 50 100.00
V2 data_fifo_status data_fifo_status 0 0 --
V2 alert_test spi_host_alert_test 21.000s 28.840us 50 50 100.00
V2 intr_test spi_host_intr_test 15.000s 20.709us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 12.000s 866.254us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 12.000s 866.254us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 14.000s 25.201us 5 5 100.00
spi_host_csr_rw 13.000s 66.234us 20 20 100.00
spi_host_csr_aliasing 5.000s 54.251us 5 5 100.00
spi_host_same_csr_outstanding 15.000s 29.123us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 14.000s 25.201us 5 5 100.00
spi_host_csr_rw 13.000s 66.234us 20 20 100.00
spi_host_csr_aliasing 5.000s 54.251us 5 5 100.00
spi_host_same_csr_outstanding 15.000s 29.123us 20 20 100.00
V2 TOTAL 686 690 99.42
V2S tl_intg_err spi_host_tl_intg_err 14.000s 353.908us 20 20 100.00
spi_host_sec_cm 3.000s 40.813us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 14.000s 353.908us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 825 830 99.40

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 15 13 81.25
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.50 96.19 92.01 98.06 96.81 95.70 100.00 98.60 90.87

Failure Buckets

Past Results