SPI_HOST Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.750m 13.915ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 17.151us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 29.297us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 4.000s 192.426us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 2.000s 39.414us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 46.739us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 29.297us 20 20 100.00
spi_host_csr_aliasing 2.000s 39.414us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 17.193us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 19.006us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 4.000s 215.374us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.383m 11.877ms 50 50 100.00
spi_host_error_cmd 7.000s 18.248us 50 50 100.00
spi_host_event 19.700m 105.886ms 50 50 100.00
V2 clock_rate spi_host_speed 6.600m 7.718ms 50 50 100.00
V2 speed spi_host_speed 6.600m 7.718ms 50 50 100.00
V2 chip_select_timing spi_host_speed 6.600m 7.718ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 10.517m 31.753ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 8.000s 513.021us 50 50 100.00
V2 cpol_cpha spi_host_speed 6.600m 7.718ms 50 50 100.00
V2 full_cycle spi_host_speed 6.600m 7.718ms 50 50 100.00
V2 duplex spi_host_smoke 10.750m 13.915ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 10.750m 13.915ms 50 50 100.00
V2 stress_all spi_host_stress_all 4.333m 12.146ms 47 50 94.00
V2 spien spi_host_spien 8.683m 10.641ms 50 50 100.00
V2 stall spi_host_status_stall 8.217m 11.674ms 47 50 94.00
V2 Idlecsbactive spi_host_idlecsbactive 44.000s 7.239ms 50 50 100.00
V2 data_fifo_status data_fifo_status 0 0 --
V2 alert_test spi_host_alert_test 12.000s 14.814us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 27.433us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 76.033us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 76.033us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 17.151us 5 5 100.00
spi_host_csr_rw 3.000s 29.297us 20 20 100.00
spi_host_csr_aliasing 2.000s 39.414us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 49.387us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 17.151us 5 5 100.00
spi_host_csr_rw 3.000s 29.297us 20 20 100.00
spi_host_csr_aliasing 2.000s 39.414us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 49.387us 20 20 100.00
V2 TOTAL 684 690 99.13
V2S tl_intg_err spi_host_tl_intg_err 4.000s 95.503us 20 20 100.00
spi_host_sec_cm 3.000s 42.260us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 95.503us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 824 830 99.28

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 15 13 81.25
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.51 96.19 92.01 98.06 96.90 95.70 100.00 98.60 90.87

Failure Buckets

Past Results