SPI_HOST Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.417m	67.465ms	46	50	92.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	67.610us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	44.268us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	901.966us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	147.789us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	39.960us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	44.268us	20	20	100.00
		spi_host_csr_aliasing	3.000s	147.789us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	19.806us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	18.728us	5	5	100.00
V1		TOTAL			111	115	96.52
V2	performance	spi_host_performance	13.000s	29.500us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.017m	15.900ms	50	50	100.00
		spi_host_error_cmd	12.000s	33.869us	50	50	100.00
		spi_host_event	18.833m	81.729ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.067m	6.490ms	50	50	100.00
V2	speed	spi_host_speed	5.067m	6.490ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.067m	6.490ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	6.067m	17.670ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	8.000s	230.324us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.067m	6.490ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.067m	6.490ms	50	50	100.00
V2	duplex	spi_host_smoke	10.417m	67.465ms	46	50	92.00
V2	tx_rx_only	spi_host_smoke	10.417m	67.465ms	46	50	92.00
V2	stress_all	spi_host_stress_all	3.417m	4.050ms	49	50	98.00
V2	spien	spi_host_spien	6.833m	80.447ms	50	50	100.00
V2	stall	spi_host_status_stall	9.767m	18.294ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	35.000s	2.738ms	50	50	100.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	12.000s	18.583us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	34.536us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	106.720us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	106.720us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	67.610us	5	5	100.00
		spi_host_csr_rw	3.000s	44.268us	20	20	100.00
		spi_host_csr_aliasing	3.000s	147.789us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	49.754us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	67.610us	5	5	100.00
		spi_host_csr_rw	3.000s	44.268us	20	20	100.00
		spi_host_csr_aliasing	3.000s	147.789us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	49.754us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	326.225us	20	20	100.00
		spi_host_sec_cm	7.000s	77.058us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	326.225us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			824	830	99.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	13	81.25
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.49	96.19	92.01	98.06	96.72	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:
- Test spi_host_smoke has 3 failures.
  - 8.spi_host_smoke.1235650334688678634647264155014628413788613701393407177139208252719966856963
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 154487115457 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x55c79bd4) == 0x0
  UVM_INFO @ 154487115457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.spi_host_smoke.20895908292026024735497159656586769349430635476511730068939528370707065927986
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 101409152537 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xed1f1054) == 0x0
  UVM_INFO @ 101409152537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:
- Test spi_host_status_stall has 1 failures.
  - 22.spi_host_status_stall.107551862686388589245117855046971315418230458029015449110319754458266211834497
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 134544655493 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf435ec54) == 0x0
  UVM_INFO @ 134544655493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 1 failures.
  - 24.spi_host_smoke.3708128113627781838430850913386980843783318534377996661422211308217293011831
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 121467224313 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe0636314) == 0x0
  UVM_INFO @ 121467224313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 1 failures.
  - 27.spi_host_stress_all.4577804394977826170289019831919585580182886343987067209780060118870024031312
    Line 299, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 12966350139 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2abfdf14) == 0x0
  UVM_INFO @ 12966350139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ecd9f08747`