SPI_HOST Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.050m	54.189ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	52.887us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	7.000s	107.293us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	474.727us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	23.880us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	42.426us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	7.000s	107.293us	20	20	100.00
		spi_host_csr_aliasing	2.000s	23.880us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	27.299us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	19.829us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	3.000s	101.470us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.400m	15.697ms	50	50	100.00
		spi_host_error_cmd	3.000s	85.642us	50	50	100.00
		spi_host_event	25.633m	38.439ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.233m	30.644ms	50	50	100.00
V2	speed	spi_host_speed	6.233m	30.644ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.233m	30.644ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	10.650m	88.244ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	236.153us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.233m	30.644ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.233m	30.644ms	50	50	100.00
V2	duplex	spi_host_smoke	10.050m	54.189ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	10.050m	54.189ms	50	50	100.00
V2	stress_all	spi_host_stress_all	3.883m	20.016ms	48	50	96.00
V2	spien	spi_host_spien	6.283m	15.747ms	49	50	98.00
V2	stall	spi_host_status_stall	9.950m	27.026ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	43.000s	16.721ms	49	50	98.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	31.260us	50	50	100.00
V2	intr_test	spi_host_intr_test	7.000s	50.688us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	8.000s	22.225us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	8.000s	22.225us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	52.887us	5	5	100.00
		spi_host_csr_rw	7.000s	107.293us	20	20	100.00
		spi_host_csr_aliasing	2.000s	23.880us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	77.547us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	52.887us	5	5	100.00
		spi_host_csr_rw	7.000s	107.293us	20	20	100.00
		spi_host_csr_aliasing	2.000s	23.880us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	77.547us	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	327.121us	20	20	100.00
		spi_host_sec_cm	3.000s	107.117us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	327.121us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			823	830	99.16

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	15	11	68.75
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.50	96.19	92.01	98.06	96.81	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
- Test spi_host_status_stall has 3 failures.
  - 2.spi_host_status_stall.61365747305550314373637334968104004736001983274509449364297923022764571048173
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 120440136458 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xeebf7254) == 0x0
  UVM_INFO @ 120440136458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.spi_host_status_stall.44929891436580018317507854028266526903740878651183488090315939568497648629233
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 94992097265 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x14b87054) == 0x0
  UVM_INFO @ 94992097265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_idlecsbactive has 1 failures.
  - 39.spi_host_idlecsbactive.69852774304676572067333331242117069080326428820984745787177793153421522646417
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10065503308 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8220e2d4) == 0x0
  UVM_INFO @ 10065503308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 6.spi_host_stress_all.93576627392333740720626233684235030992376061780414658540219808337861404678723
    Line 297, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 13526597334 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8c87bb94) == 0x0
  UVM_INFO @ 13526597334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 7.spi_host_stress_all.21277995681643657969098266289670946464804749174434461143017800150157741554558
    Line 316, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10428470177 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x57e99ad4) == 0x0
  UVM_INFO @ 10428470177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 37.spi_host_spien.18396681752717065974279709048264216896423322669694934121188534472393339237717
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 66445462536 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x51b3cc14) == 0x1
  UVM_INFO @ 66445462536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d0c52cdadd`