SPI_HOST Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.717m 146.590ms 49 50 98.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 25.384us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 21.662us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 4.000s 206.447us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 101.273us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 127.185us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 21.662us 20 20 100.00
spi_host_csr_aliasing 3.000s 101.273us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 17.879us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 43.595us 5 5 100.00
V1 TOTAL 114 115 99.13
V2 performance spi_host_performance 4.000s 33.327us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.600m 6.245ms 50 50 100.00
spi_host_error_cmd 3.000s 39.113us 50 50 100.00
spi_host_event 27.167m 39.008ms 50 50 100.00
V2 clock_rate spi_host_speed 8.000m 10.228ms 50 50 100.00
V2 speed spi_host_speed 8.000m 10.228ms 50 50 100.00
V2 chip_select_timing spi_host_speed 8.000m 10.228ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 6.167m 16.603ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 3.000s 398.052us 50 50 100.00
V2 cpol_cpha spi_host_speed 8.000m 10.228ms 50 50 100.00
V2 full_cycle spi_host_speed 8.000m 10.228ms 50 50 100.00
V2 duplex spi_host_smoke 10.717m 146.590ms 49 50 98.00
V2 tx_rx_only spi_host_smoke 10.717m 146.590ms 49 50 98.00
V2 stress_all spi_host_stress_all 3.783m 16.288ms 50 50 100.00
V2 spien spi_host_spien 5.950m 32.176ms 49 50 98.00
V2 stall spi_host_status_stall 9.750m 51.726ms 46 50 92.00
V2 Idlecsbactive spi_host_idlecsbactive 45.000s 6.536ms 50 50 100.00
V2 data_fifo_status data_fifo_status 0 0 --
V2 alert_test spi_host_alert_test 3.000s 68.650us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 17.067us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 4.000s 281.371us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 4.000s 281.371us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 25.384us 5 5 100.00
spi_host_csr_rw 3.000s 21.662us 20 20 100.00
spi_host_csr_aliasing 3.000s 101.273us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 69.076us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 25.384us 5 5 100.00
spi_host_csr_rw 3.000s 21.662us 20 20 100.00
spi_host_csr_aliasing 3.000s 101.273us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 69.076us 20 20 100.00
V2 TOTAL 685 690 99.28
V2S tl_intg_err spi_host_tl_intg_err 4.000s 561.108us 20 20 100.00
spi_host_sec_cm 3.000s 61.569us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 561.108us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 824 830 99.28

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 15 13 81.25
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.50 96.19 92.01 98.06 96.81 95.70 100.00 98.60 90.87

Failure Buckets

Past Results