18c8953cf1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 10.717m | 146.590ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 25.384us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 21.662us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 4.000s | 206.447us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 101.273us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 127.185us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 21.662us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 101.273us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 17.879us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 2.000s | 43.595us | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | performance | spi_host_performance | 4.000s | 33.327us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.600m | 6.245ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 3.000s | 39.113us | 50 | 50 | 100.00 | ||
| spi_host_event | 27.167m | 39.008ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 8.000m | 10.228ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 8.000m | 10.228ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 8.000m | 10.228ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 6.167m | 16.603ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 3.000s | 398.052us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 8.000m | 10.228ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 8.000m | 10.228ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 10.717m | 146.590ms | 49 | 50 | 98.00 |
| V2 | tx_rx_only | spi_host_smoke | 10.717m | 146.590ms | 49 | 50 | 98.00 |
| V2 | stress_all | spi_host_stress_all | 3.783m | 16.288ms | 50 | 50 | 100.00 |
| V2 | spien | spi_host_spien | 5.950m | 32.176ms | 49 | 50 | 98.00 |
| V2 | stall | spi_host_status_stall | 9.750m | 51.726ms | 46 | 50 | 92.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 45.000s | 6.536ms | 50 | 50 | 100.00 |
| V2 | data_fifo_status | data_fifo_status | 0 | 0 | -- | ||
| V2 | alert_test | spi_host_alert_test | 3.000s | 68.650us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 17.067us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 4.000s | 281.371us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 4.000s | 281.371us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 25.384us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 21.662us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 101.273us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 69.076us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 25.384us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 21.662us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 101.273us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 69.076us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 685 | 690 | 99.28 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 561.108us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 61.569us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 561.108us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 824 | 830 | 99.28 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 15 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 96.50 | 96.19 | 92.01 | 98.06 | 96.81 | 95.70 | 100.00 | 98.60 | 90.87 |
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
3.spi_host_status_stall.111172573472373990806156732044135753151718744769836150070597814494261856091940
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log
UVM_FATAL @ 66196379340 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x757a7e94) == 0x0
UVM_INFO @ 66196379340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.spi_host_status_stall.37943704645130968765362843213168053672691406925939602604216254492651946596143
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_status_stall/latest/run.log
UVM_FATAL @ 147506956241 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb92d9614) == 0x0
UVM_INFO @ 147506956241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
Test spi_host_status_stall has 1 failures.
23.spi_host_status_stall.2621187551292025344904930392904542055578838077881844969000763613963375300118
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_status_stall/latest/run.log
UVM_FATAL @ 25878612373 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3aaed294) == 0x1
UVM_INFO @ 25878612373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
36.spi_host_spien.21016368585358872394859059262745583442395481716720527796234682637242326203107
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_spien/latest/run.log
UVM_FATAL @ 24952789558 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x24be3914) == 0x1
UVM_INFO @ 24952789558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
Test spi_host_smoke has 1 failures.
45.spi_host_smoke.37159841967596523661657319341301713607576618764919751596172354712156089412310
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_smoke/latest/run.log
UVM_FATAL @ 146589508549 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5cd68b94) == 0x0
UVM_INFO @ 146589508549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
45.spi_host_status_stall.17598258184962120117997753224172768704682442816478188814693627933802858288712
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_status_stall/latest/run.log
UVM_FATAL @ 164223329652 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5f353bd4) == 0x0
UVM_INFO @ 164223329652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---