SPI_HOST Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.333m	61.437ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	73.051us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	33.702us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	620.033us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	87.086us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	84.507us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	33.702us	20	20	100.00
		spi_host_csr_aliasing	3.000s	87.086us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	44.880us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	205.341us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	4.000s	29.075us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.717m	7.028ms	50	50	100.00
		spi_host_error_cmd	3.000s	87.046us	50	50	100.00
		spi_host_event	16.717m	372.640ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.667m	28.215ms	50	50	100.00
V2	speed	spi_host_speed	5.667m	28.215ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.667m	28.215ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.683m	8.349ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	710.551us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.667m	28.215ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.667m	28.215ms	50	50	100.00
V2	duplex	spi_host_smoke	10.333m	61.437ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	10.333m	61.437ms	48	50	96.00
V2	stress_all	spi_host_stress_all	4.283m	10.002ms	49	50	98.00
V2	spien	spi_host_spien	7.983m	67.548ms	49	50	98.00
V2	stall	spi_host_status_stall	9.417m	24.312ms	44	50	88.00
V2	Idlecsbactive	spi_host_idlecsbactive	46.000s	8.036ms	50	50	100.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	52.117us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	22.644us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	51.750us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	51.750us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	73.051us	5	5	100.00
		spi_host_csr_rw	3.000s	33.702us	20	20	100.00
		spi_host_csr_aliasing	3.000s	87.086us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	32.036us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	73.051us	5	5	100.00
		spi_host_csr_rw	3.000s	33.702us	20	20	100.00
		spi_host_csr_aliasing	3.000s	87.086us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	32.036us	20	20	100.00
V2		TOTAL			682	690	98.84
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	100.840us	20	20	100.00
		spi_host_sec_cm	3.000s	44.914us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	100.840us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			820	830	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	12	75.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.48	96.19	92.01	98.06	96.63	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 7 failures:
- Test spi_host_smoke has 2 failures.
  - 2.spi_host_smoke.1108251915186388396893418750686809748213778829806293856349055040441324598339
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 96813968563 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x842e3c14) == 0x0
  UVM_INFO @ 96813968563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.spi_host_smoke.5250827541374471006100649313404915025982875608739192935257224436211671738301
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 105430076395 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe1210cd4) == 0x0
  UVM_INFO @ 105430076395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 5 failures.
  - 10.spi_host_status_stall.80777459412879022418827641664147499910556420265420674104836988947312093751597
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 158481017238 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd61283d4) == 0x0
  UVM_INFO @ 158481017238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.spi_host_status_stall.100329314044561732250176762793284566960470356486777552883726665704046880350111
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 151113465498 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2516814) == 0x0
  UVM_INFO @ 151113465498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 7.spi_host_status_stall.36071666776148998938007914773072347687747869727657020590826059069888491336596
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 54263010843 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xccbbd1d4) == 0x0
  UVM_INFO @ 54263010843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 12.spi_host_stress_all.29496474691710936479986845602809253365944353500238709129470359545044808774557
    Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10001606536 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xac74ed54) == 0x0
  UVM_INFO @ 10001606536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 28.spi_host_spien.44784599965910617579306441571881951083466376269860687288071598183342238825301
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 10016460721 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdaee10d4) == 0x0
  UVM_INFO @ 10016460721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9656691e03`