SPI_HOST Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.333m 61.437ms 48 50 96.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 73.051us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 33.702us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 4.000s 620.033us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 87.086us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 84.507us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 33.702us 20 20 100.00
spi_host_csr_aliasing 3.000s 87.086us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 44.880us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 205.341us 5 5 100.00
V1 TOTAL 113 115 98.26
V2 performance spi_host_performance 4.000s 29.075us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.717m 7.028ms 50 50 100.00
spi_host_error_cmd 3.000s 87.046us 50 50 100.00
spi_host_event 16.717m 372.640ms 50 50 100.00
V2 clock_rate spi_host_speed 5.667m 28.215ms 50 50 100.00
V2 speed spi_host_speed 5.667m 28.215ms 50 50 100.00
V2 chip_select_timing spi_host_speed 5.667m 28.215ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 4.683m 8.349ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 710.551us 50 50 100.00
V2 cpol_cpha spi_host_speed 5.667m 28.215ms 50 50 100.00
V2 full_cycle spi_host_speed 5.667m 28.215ms 50 50 100.00
V2 duplex spi_host_smoke 10.333m 61.437ms 48 50 96.00
V2 tx_rx_only spi_host_smoke 10.333m 61.437ms 48 50 96.00
V2 stress_all spi_host_stress_all 4.283m 10.002ms 49 50 98.00
V2 spien spi_host_spien 7.983m 67.548ms 49 50 98.00
V2 stall spi_host_status_stall 9.417m 24.312ms 44 50 88.00
V2 Idlecsbactive spi_host_idlecsbactive 46.000s 8.036ms 50 50 100.00
V2 data_fifo_status data_fifo_status 0 0 --
V2 alert_test spi_host_alert_test 3.000s 52.117us 50 50 100.00
V2 intr_test spi_host_intr_test 4.000s 22.644us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 51.750us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 51.750us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 73.051us 5 5 100.00
spi_host_csr_rw 3.000s 33.702us 20 20 100.00
spi_host_csr_aliasing 3.000s 87.086us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 32.036us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 73.051us 5 5 100.00
spi_host_csr_rw 3.000s 33.702us 20 20 100.00
spi_host_csr_aliasing 3.000s 87.086us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 32.036us 20 20 100.00
V2 TOTAL 682 690 98.84
V2S tl_intg_err spi_host_tl_intg_err 4.000s 100.840us 20 20 100.00
spi_host_sec_cm 3.000s 44.914us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 100.840us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 820 830 98.80

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 15 12 75.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.48 96.19 92.01 98.06 96.63 95.70 100.00 98.60 90.87

Failure Buckets

Past Results