SPI_HOST Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 9.550m 49.182ms 49 50 98.00
V1 csr_hw_reset spi_host_csr_hw_reset 11.000s 29.728us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 46.012us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 8.000s 89.968us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 98.090us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 8.000s 37.397us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 46.012us 20 20 100.00
spi_host_csr_aliasing 3.000s 98.090us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 14.991us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 55.344us 5 5 100.00
V1 TOTAL 114 115 99.13
V2 performance spi_host_performance 12.000s 252.784us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 4.100m 9.914ms 49 50 98.00
spi_host_error_cmd 8.000s 34.611us 50 50 100.00
spi_host_event 13.717m 38.877ms 50 50 100.00
V2 clock_rate spi_host_speed 5.950m 7.591ms 50 50 100.00
V2 speed spi_host_speed 5.950m 7.591ms 50 50 100.00
V2 chip_select_timing spi_host_speed 5.950m 7.591ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 9.133m 20.772ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 13.000s 171.368us 50 50 100.00
V2 cpol_cpha spi_host_speed 5.950m 7.591ms 50 50 100.00
V2 full_cycle spi_host_speed 5.950m 7.591ms 50 50 100.00
V2 duplex spi_host_smoke 9.550m 49.182ms 49 50 98.00
V2 tx_rx_only spi_host_smoke 9.550m 49.182ms 49 50 98.00
V2 stress_all spi_host_stress_all 3.817m 10.001ms 45 50 90.00
V2 spien spi_host_spien 6.517m 35.459ms 50 50 100.00
V2 stall spi_host_status_stall 12.617m 19.475ms 44 50 88.00
V2 Idlecsbactive spi_host_idlecsbactive 45.000s 9.269ms 50 50 100.00
V2 data_fifo_status data_fifo_status 0 0 --
V2 alert_test spi_host_alert_test 16.000s 17.773us 50 50 100.00
V2 intr_test spi_host_intr_test 12.000s 44.695us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 112.119us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 112.119us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 11.000s 29.728us 5 5 100.00
spi_host_csr_rw 3.000s 46.012us 20 20 100.00
spi_host_csr_aliasing 3.000s 98.090us 5 5 100.00
spi_host_same_csr_outstanding 12.000s 22.730us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 11.000s 29.728us 5 5 100.00
spi_host_csr_rw 3.000s 46.012us 20 20 100.00
spi_host_csr_aliasing 3.000s 98.090us 5 5 100.00
spi_host_same_csr_outstanding 12.000s 22.730us 20 20 100.00
V2 TOTAL 678 690 98.26
V2S tl_intg_err spi_host_tl_intg_err 8.000s 315.613us 20 20 100.00
spi_host_sec_cm 3.000s 40.508us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 8.000s 315.613us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 817 830 98.43

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 15 12 75.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.54 96.28 92.20 98.06 96.81 95.70 100.00 98.60 90.87

Failure Buckets

Past Results