69c572b503| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 9.550m | 49.182ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 11.000s | 29.728us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 46.012us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 8.000s | 89.968us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 98.090us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 8.000s | 37.397us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 46.012us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 98.090us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 14.991us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 55.344us | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | performance | spi_host_performance | 12.000s | 252.784us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 4.100m | 9.914ms | 49 | 50 | 98.00 |
| spi_host_error_cmd | 8.000s | 34.611us | 50 | 50 | 100.00 | ||
| spi_host_event | 13.717m | 38.877ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 5.950m | 7.591ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 5.950m | 7.591ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 5.950m | 7.591ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 9.133m | 20.772ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 13.000s | 171.368us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 5.950m | 7.591ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 5.950m | 7.591ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 9.550m | 49.182ms | 49 | 50 | 98.00 |
| V2 | tx_rx_only | spi_host_smoke | 9.550m | 49.182ms | 49 | 50 | 98.00 |
| V2 | stress_all | spi_host_stress_all | 3.817m | 10.001ms | 45 | 50 | 90.00 |
| V2 | spien | spi_host_spien | 6.517m | 35.459ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 12.617m | 19.475ms | 44 | 50 | 88.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 45.000s | 9.269ms | 50 | 50 | 100.00 |
| V2 | data_fifo_status | data_fifo_status | 0 | 0 | -- | ||
| V2 | alert_test | spi_host_alert_test | 16.000s | 17.773us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 12.000s | 44.695us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 112.119us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 112.119us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 11.000s | 29.728us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 46.012us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 98.090us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 12.000s | 22.730us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 11.000s | 29.728us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 46.012us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 98.090us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 12.000s | 22.730us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 678 | 690 | 98.26 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 8.000s | 315.613us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 40.508us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 8.000s | 315.613us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 817 | 830 | 98.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 15 | 12 | 75.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 96.54 | 96.28 | 92.20 | 98.06 | 96.81 | 95.70 | 100.00 | 98.60 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 7 failures:
Test spi_host_overflow_underflow has 1 failures.
0.spi_host_overflow_underflow.17123363804803551284961352475610291569725640266231696343076057470254073245272
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 27956404315 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3a0ce3d4) == 0x0
UVM_INFO @ 27956404315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
17.spi_host_smoke.80770782791542825036157634613058099146506243150506116748570735593279314788512
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_smoke/latest/run.log
UVM_FATAL @ 156841275626 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf8c39a54) == 0x0
UVM_INFO @ 156841275626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 2 failures.
24.spi_host_stress_all.3252528831037908226836500257945912930619348003991726053910114836846002594060
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_stress_all/latest/run.log
UVM_FATAL @ 17626640861 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7cbfa694) == 0x0
UVM_INFO @ 17626640861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.spi_host_stress_all.6901833478694601240320329208743189216356749402688608382543538816931695045295
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_stress_all/latest/run.log
UVM_FATAL @ 14871393505 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4b00bd54) == 0x0
UVM_INFO @ 14871393505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 3 failures.
34.spi_host_status_stall.42649344034984601307408831478756698254417684996727270360644840676705992560885
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_status_stall/latest/run.log
UVM_FATAL @ 61752131078 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8adb6394) == 0x0
UVM_INFO @ 61752131078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.spi_host_status_stall.38304393670499332088344330114049078579328324331499752749227466551074970078354
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_status_stall/latest/run.log
UVM_FATAL @ 73602548813 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x49677b94) == 0x0
UVM_INFO @ 73602548813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:
8.spi_host_stress_all.113652285407948570579704667746141785698302172914912521766966468257236189708310
Line 299, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10050428364 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8afd7594) == 0x0
UVM_INFO @ 10050428364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.spi_host_stress_all.54849869074143794114458187264122708711365562452387747482631500829162696497715
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10000996505 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe68b2d4) == 0x0
UVM_INFO @ 10000996505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
6.spi_host_status_stall.105821117058773284479249130354731746023445660663235063094224915315158987686120
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_status_stall/latest/run.log
UVM_FATAL @ 184776968998 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcf56c154) == 0x0
UVM_INFO @ 184776968998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
25.spi_host_status_stall.98629298587427691313286726940233877617391079306207074799232445362649462150636
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_status_stall/latest/run.log
UVM_FATAL @ 11178986181 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x51852c54) == 0x1
UVM_INFO @ 11178986181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
47.spi_host_stress_all.33390215588644435341643569537301296053271687998938146265795718653896221068959
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_stress_all/latest/run.log
UVM_FATAL @ 23451194863 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x160617d4) == 0x0
UVM_INFO @ 23451194863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
48.spi_host_status_stall.79561017491835876686116866095174666930142425024766459693749019456467147967227
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_status_stall/latest/run.log
UVM_FATAL @ 19474505566 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x76f156d4) == 0x1
UVM_INFO @ 19474505566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---