SPI_HOST Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	11.933m	62.796ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	7.000s	134.412us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	7.000s	22.646us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	8.000s	376.406us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	13.000s	56.096us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	13.000s	56.555us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	7.000s	22.646us	20	20	100.00
		spi_host_csr_aliasing	13.000s	56.096us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	31.443us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	23.297us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	13.000s	29.693us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.183m	4.019ms	50	50	100.00
		spi_host_error_cmd	13.000s	18.948us	50	50	100.00
		spi_host_event	20.933m	61.949ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.800m	64.228ms	50	50	100.00
V2	speed	spi_host_speed	5.800m	64.228ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.800m	64.228ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.700m	8.824ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	8.000s	291.068us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.800m	64.228ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.800m	64.228ms	50	50	100.00
V2	duplex	spi_host_smoke	11.933m	62.796ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	11.933m	62.796ms	49	50	98.00
V2	stress_all	spi_host_stress_all	4.317m	5.516ms	45	50	90.00
V2	spien	spi_host_spien	6.967m	85.672ms	49	50	98.00
V2	stall	spi_host_status_stall	8.517m	24.049ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	47.000s	7.476ms	50	50	100.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	7.000s	25.221us	50	50	100.00
V2	intr_test	spi_host_intr_test	7.000s	18.504us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	10.000s	1.494ms	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	10.000s	1.494ms	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	7.000s	134.412us	5	5	100.00
		spi_host_csr_rw	7.000s	22.646us	20	20	100.00
		spi_host_csr_aliasing	13.000s	56.096us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	25.966us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	7.000s	134.412us	5	5	100.00
		spi_host_csr_rw	7.000s	22.646us	20	20	100.00
		spi_host_csr_aliasing	13.000s	56.096us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	25.966us	20	20	100.00
V2		TOTAL			681	690	98.70
V2S	tl_intg_err	spi_host_tl_intg_err	12.000s	53.420us	20	20	100.00
		spi_host_sec_cm	3.000s	62.287us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	12.000s	53.420us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			820	830	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	12	75.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.48	96.18	92.00	98.06	96.71	95.70	100.00	98.60	90.46

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
- Test spi_host_stress_all has 3 failures.
  - 12.spi_host_stress_all.74606916464695392148558436933515163770648541218858505775594992253812286759721
    Line 297, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 15473941956 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6a4ff014) == 0x0
  UVM_INFO @ 15473941956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.spi_host_stress_all.37520178148083418868446316848197550663568655569951635076259439704152698908474
    Line 297, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 15037945589 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xad8fc754) == 0x0
  UVM_INFO @ 15037945589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_smoke has 1 failures.
  - 46.spi_host_smoke.64820494337300923530972387863862367049714553202687534941027760744763030659489
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 99648666421 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x36029f94) == 0x0
  UVM_INFO @ 99648666421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 3 failures:
- Test spi_host_status_stall has 3 failures.
  - 14.spi_host_status_stall.2458749766563424628079840274685001844845443232116920439170926582460981779574
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 28559966381 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc57da94) == 0x1
  UVM_INFO @ 28559966381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.spi_host_status_stall.44769690954375784362140694319017497963890359317105827965963035167865805198402
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 44545248684 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3ee90114) == 0x1
  UVM_INFO @ 44545248684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
- Test spi_host_stress_all has 2 failures.
  - 0.spi_host_stress_all.89136108040918075316366863516142877193439419794318167016694083676082182932020
    Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 14641709505 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x906653d4) == 0x0
  UVM_INFO @ 14641709505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.spi_host_stress_all.68766891039196527185768774681767772905274595254960421537967910458575947469994
    Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 33799029077 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x72c9454) == 0x0
  UVM_INFO @ 33799029077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 22.spi_host_spien.89439085481786199267594580320832317025099958223854381934247671263580672671795
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 68248303695 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5c72ba94) == 0x1
  UVM_INFO @ 68248303695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `00fe426038`