SPI_HOST Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 11.933m 62.796ms 49 50 98.00
V1 csr_hw_reset spi_host_csr_hw_reset 7.000s 134.412us 5 5 100.00
V1 csr_rw spi_host_csr_rw 7.000s 22.646us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 8.000s 376.406us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 13.000s 56.096us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 13.000s 56.555us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 7.000s 22.646us 20 20 100.00
spi_host_csr_aliasing 13.000s 56.096us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 31.443us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 23.297us 5 5 100.00
V1 TOTAL 114 115 99.13
V2 performance spi_host_performance 13.000s 29.693us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.183m 4.019ms 50 50 100.00
spi_host_error_cmd 13.000s 18.948us 50 50 100.00
spi_host_event 20.933m 61.949ms 50 50 100.00
V2 clock_rate spi_host_speed 5.800m 64.228ms 50 50 100.00
V2 speed spi_host_speed 5.800m 64.228ms 50 50 100.00
V2 chip_select_timing spi_host_speed 5.800m 64.228ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 4.700m 8.824ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 8.000s 291.068us 50 50 100.00
V2 cpol_cpha spi_host_speed 5.800m 64.228ms 50 50 100.00
V2 full_cycle spi_host_speed 5.800m 64.228ms 50 50 100.00
V2 duplex spi_host_smoke 11.933m 62.796ms 49 50 98.00
V2 tx_rx_only spi_host_smoke 11.933m 62.796ms 49 50 98.00
V2 stress_all spi_host_stress_all 4.317m 5.516ms 45 50 90.00
V2 spien spi_host_spien 6.967m 85.672ms 49 50 98.00
V2 stall spi_host_status_stall 8.517m 24.049ms 47 50 94.00
V2 Idlecsbactive spi_host_idlecsbactive 47.000s 7.476ms 50 50 100.00
V2 data_fifo_status data_fifo_status 0 0 --
V2 alert_test spi_host_alert_test 7.000s 25.221us 50 50 100.00
V2 intr_test spi_host_intr_test 7.000s 18.504us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 10.000s 1.494ms 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 10.000s 1.494ms 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 7.000s 134.412us 5 5 100.00
spi_host_csr_rw 7.000s 22.646us 20 20 100.00
spi_host_csr_aliasing 13.000s 56.096us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 25.966us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 7.000s 134.412us 5 5 100.00
spi_host_csr_rw 7.000s 22.646us 20 20 100.00
spi_host_csr_aliasing 13.000s 56.096us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 25.966us 20 20 100.00
V2 TOTAL 681 690 98.70
V2S tl_intg_err spi_host_tl_intg_err 12.000s 53.420us 20 20 100.00
spi_host_sec_cm 3.000s 62.287us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 12.000s 53.420us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 820 830 98.80

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 15 12 75.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.48 96.18 92.00 98.06 96.71 95.70 100.00 98.60 90.46

Failure Buckets

Past Results