SPI_HOST Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.750m 28.762ms 47 50 94.00
V1 csr_hw_reset spi_host_csr_hw_reset 4.000s 17.904us 5 5 100.00
V1 csr_rw spi_host_csr_rw 12.000s 27.431us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 4.000s 2.429ms 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 7.000s 63.477us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 13.000s 37.754us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 12.000s 27.431us 20 20 100.00
spi_host_csr_aliasing 7.000s 63.477us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 20.849us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 16.970us 5 5 100.00
V1 TOTAL 112 115 97.39
V2 performance spi_host_performance 12.000s 54.703us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.883m 10.151ms 50 50 100.00
spi_host_error_cmd 7.000s 21.269us 50 50 100.00
spi_host_event 19.900m 386.918ms 50 50 100.00
V2 clock_rate spi_host_speed 4.333m 13.362ms 50 50 100.00
V2 speed spi_host_speed 4.333m 13.362ms 50 50 100.00
V2 chip_select_timing spi_host_speed 4.333m 13.362ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 5.350m 20.493ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 8.000s 180.162us 50 50 100.00
V2 cpol_cpha spi_host_speed 4.333m 13.362ms 50 50 100.00
V2 full_cycle spi_host_speed 4.333m 13.362ms 50 50 100.00
V2 duplex spi_host_smoke 10.750m 28.762ms 47 50 94.00
V2 tx_rx_only spi_host_smoke 10.750m 28.762ms 47 50 94.00
V2 stress_all spi_host_stress_all 2.733m 7.967ms 50 50 100.00
V2 spien spi_host_spien 6.633m 33.533ms 49 50 98.00
V2 stall spi_host_status_stall 9.733m 17.728ms 48 50 96.00
V2 Idlecsbactive spi_host_idlecsbactive 46.000s 17.152ms 50 50 100.00
V2 data_fifo_status data_fifo_status 0 0 --
V2 alert_test spi_host_alert_test 8.000s 165.824us 50 50 100.00
V2 intr_test spi_host_intr_test 7.000s 115.434us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 9.000s 37.165us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 9.000s 37.165us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 4.000s 17.904us 5 5 100.00
spi_host_csr_rw 12.000s 27.431us 20 20 100.00
spi_host_csr_aliasing 7.000s 63.477us 5 5 100.00
spi_host_same_csr_outstanding 8.000s 18.486us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 4.000s 17.904us 5 5 100.00
spi_host_csr_rw 12.000s 27.431us 20 20 100.00
spi_host_csr_aliasing 7.000s 63.477us 5 5 100.00
spi_host_same_csr_outstanding 8.000s 18.486us 20 20 100.00
V2 TOTAL 687 690 99.57
V2S tl_intg_err spi_host_tl_intg_err 10.000s 307.275us 20 20 100.00
spi_host_sec_cm 3.000s 265.508us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 10.000s 307.275us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 824 830 99.28

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 15 13 81.25
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.51 96.18 92.00 98.06 96.89 95.70 100.00 98.60 90.87

Failure Buckets

Past Results