SPI_HOST Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.750m	28.762ms	47	50	94.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	17.904us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	12.000s	27.431us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	2.429ms	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	7.000s	63.477us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	13.000s	37.754us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	12.000s	27.431us	20	20	100.00
		spi_host_csr_aliasing	7.000s	63.477us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	20.849us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	16.970us	5	5	100.00
V1		TOTAL			112	115	97.39
V2	performance	spi_host_performance	12.000s	54.703us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.883m	10.151ms	50	50	100.00
		spi_host_error_cmd	7.000s	21.269us	50	50	100.00
		spi_host_event	19.900m	386.918ms	50	50	100.00
V2	clock_rate	spi_host_speed	4.333m	13.362ms	50	50	100.00
V2	speed	spi_host_speed	4.333m	13.362ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	4.333m	13.362ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	5.350m	20.493ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	8.000s	180.162us	50	50	100.00
V2	cpol_cpha	spi_host_speed	4.333m	13.362ms	50	50	100.00
V2	full_cycle	spi_host_speed	4.333m	13.362ms	50	50	100.00
V2	duplex	spi_host_smoke	10.750m	28.762ms	47	50	94.00
V2	tx_rx_only	spi_host_smoke	10.750m	28.762ms	47	50	94.00
V2	stress_all	spi_host_stress_all	2.733m	7.967ms	50	50	100.00
V2	spien	spi_host_spien	6.633m	33.533ms	49	50	98.00
V2	stall	spi_host_status_stall	9.733m	17.728ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	46.000s	17.152ms	50	50	100.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	8.000s	165.824us	50	50	100.00
V2	intr_test	spi_host_intr_test	7.000s	115.434us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	9.000s	37.165us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	9.000s	37.165us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	17.904us	5	5	100.00
		spi_host_csr_rw	12.000s	27.431us	20	20	100.00
		spi_host_csr_aliasing	7.000s	63.477us	5	5	100.00
		spi_host_same_csr_outstanding	8.000s	18.486us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	17.904us	5	5	100.00
		spi_host_csr_rw	12.000s	27.431us	20	20	100.00
		spi_host_csr_aliasing	7.000s	63.477us	5	5	100.00
		spi_host_same_csr_outstanding	8.000s	18.486us	20	20	100.00
V2		TOTAL			687	690	99.57
V2S	tl_intg_err	spi_host_tl_intg_err	10.000s	307.275us	20	20	100.00
		spi_host_sec_cm	3.000s	265.508us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	10.000s	307.275us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			824	830	99.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	13	81.25
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.51	96.18	92.00	98.06	96.89	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:
- Test spi_host_smoke has 2 failures.
  - 4.spi_host_smoke.41144067308150985204268745393452757313328833217963546741421760396159686269363
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 154354835284 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x574bea14) == 0x0
  UVM_INFO @ 154354835284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.spi_host_smoke.68185942465687574884494742130484665133759759661953060761701709496562495324787
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 137975811620 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa903ffd4) == 0x0
  UVM_INFO @ 137975811620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 30.spi_host_status_stall.30083066125119234324145560480065841426481701164911935697349476698795465144602
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 114121480111 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6f9daa54) == 0x0
  UVM_INFO @ 114121480111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
- Test spi_host_status_stall has 1 failures.
  - 34.spi_host_status_stall.72033748230951850245686638947112443654445263780996072793431075380348783942058
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 37505131342 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc40fe054) == 0x1
  UVM_INFO @ 37505131342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_spien has 1 failures.
  - 42.spi_host_spien.17271096196753441337633449497338024459592432469342510232861307330750306012115
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 29323813507 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf6e01154) == 0x1
  UVM_INFO @ 29323813507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 0.spi_host_smoke.35744357558651342959618761149841329487513562167353220286969782590784798928022
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 72312415964 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc0e13d54) == 0x0
  UVM_INFO @ 72312415964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `349bab6601`