SPI_HOST Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.783m	15.038ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	17.422us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	12.000s	15.073us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	219.965us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	19.855us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	7.000s	142.607us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	12.000s	15.073us	20	20	100.00
		spi_host_csr_aliasing	3.000s	19.855us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	14.706us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	19.901us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	3.000s	58.695us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.617m	12.061ms	49	50	98.00
		spi_host_error_cmd	3.000s	17.950us	50	50	100.00
		spi_host_event	18.183m	24.364ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.650m	25.128ms	50	50	100.00
V2	speed	spi_host_speed	5.650m	25.128ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.650m	25.128ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	18.267m	59.777ms	49	50	98.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	620.441us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.650m	25.128ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.650m	25.128ms	50	50	100.00
V2	duplex	spi_host_smoke	10.783m	15.038ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	10.783m	15.038ms	48	50	96.00
V2	stress_all	spi_host_stress_all	3.167m	23.764ms	49	50	98.00
V2	spien	spi_host_spien	7.183m	9.424ms	49	50	98.00
V2	stall	spi_host_status_stall	9.817m	27.020ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	47.000s	7.049ms	49	50	98.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	17.252us	50	50	100.00
V2	intr_test	spi_host_intr_test	12.000s	59.912us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	10.000s	45.452us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	10.000s	45.452us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	17.422us	5	5	100.00
		spi_host_csr_rw	12.000s	15.073us	20	20	100.00
		spi_host_csr_aliasing	3.000s	19.855us	5	5	100.00
		spi_host_same_csr_outstanding	12.000s	20.133us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	17.422us	5	5	100.00
		spi_host_csr_rw	12.000s	15.073us	20	20	100.00
		spi_host_csr_aliasing	3.000s	19.855us	5	5	100.00
		spi_host_same_csr_outstanding	12.000s	20.133us	20	20	100.00
V2		TOTAL			682	690	98.84
V2S	tl_intg_err	spi_host_tl_intg_err	14.000s	263.969us	20	20	100.00
		spi_host_sec_cm	8.000s	1.484ms	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	14.000s	263.969us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			820	830	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	9	56.25
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.50	96.18	92.00	98.06	96.80	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 6 failures:
- Test spi_host_idlecsbactive has 1 failures.
  - 1.spi_host_idlecsbactive.44158541456146677076052641998618614933918888624232395324655719448640331098750
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10031781719 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc74f1c14) == 0x0
  UVM_INFO @ 10031781719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 7.spi_host_status_stall.9965279986646271042478449945425956431971563573948581830586372803725195164147
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 151161768498 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xfc57ae94) == 0x0
  UVM_INFO @ 151161768498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 2 failures.
  - 17.spi_host_smoke.8960448099602750115166924967263576488136912993938321273079175249426500377669
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 69749788652 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcde3acd4) == 0x0
  UVM_INFO @ 69749788652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.spi_host_smoke.22394858536941509749828731344770167394426101897833803113514400862053510827712
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 96939292770 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe48fb54) == 0x0
  UVM_INFO @ 96939292770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_sw_reset has 1 failures.
  - 17.spi_host_sw_reset.102376305829503751204409259165112159973888605474537436188103480015295173910247
    Line 364, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 59777131019 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x905f2314) == 0x0
  UVM_INFO @ 59777131019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_overflow_underflow has 1 failures.
  - 17.spi_host_overflow_underflow.14213636224182159485613529550449943426865353186281014924671812503149833413170
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 56160807638 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb33044d4) == 0x0
  UVM_INFO @ 56160807638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
- Test spi_host_stress_all has 1 failures.
  - 2.spi_host_stress_all.48112887719147309341665162460061494329866300742698679190552120362523786295607
    Line 317, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 23764208099 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xaacff854) == 0x0
  UVM_INFO @ 23764208099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 25.spi_host_status_stall.88315814327255339625948540442668463954769423743388687407711349002581310821652
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 184109826207 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc4ed294) == 0x0
  UVM_INFO @ 184109826207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 6.spi_host_status_stall.91170078025566112371694702826014345269634565332151768295984071011777088472833
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 75149528968 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2d8dff54) == 0x1
  UVM_INFO @ 75149528968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 32.spi_host_spien.73574071763777368689703234398655983081377094228166121112108177933657975753229
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 10022529061 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbe007154) == 0x0
  UVM_INFO @ 10022529061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eb776817a5`