SPI_HOST Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.350m	37.477ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	93.759us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	7.000s	30.383us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	216.389us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	47.914us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	8.000s	131.857us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	7.000s	30.383us	20	20	100.00
		spi_host_csr_aliasing	3.000s	47.914us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	21.509us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	61.795us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	4.000s	179.819us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000m	13.453ms	50	50	100.00
		spi_host_error_cmd	3.000s	18.266us	50	50	100.00
		spi_host_event	16.867m	99.269ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.483m	26.966ms	50	50	100.00
V2	speed	spi_host_speed	5.483m	26.966ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.483m	26.966ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.450m	8.048ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	178.558us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.483m	26.966ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.483m	26.966ms	50	50	100.00
V2	duplex	spi_host_smoke	10.350m	37.477ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	10.350m	37.477ms	48	50	96.00
V2	stress_all	spi_host_stress_all	3.600m	13.688ms	48	50	96.00
V2	spien	spi_host_spien	7.500m	11.711ms	49	50	98.00
V2	stall	spi_host_status_stall	9.117m	120.387ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	46.000s	6.400ms	50	50	100.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	60.017us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	57.526us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	396.803us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	396.803us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	93.759us	5	5	100.00
		spi_host_csr_rw	7.000s	30.383us	20	20	100.00
		spi_host_csr_aliasing	3.000s	47.914us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	52.090us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	93.759us	5	5	100.00
		spi_host_csr_rw	7.000s	30.383us	20	20	100.00
		spi_host_csr_aliasing	3.000s	47.914us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	52.090us	20	20	100.00
V2		TOTAL			685	690	99.28
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	325.826us	20	20	100.00
		spi_host_sec_cm	2.000s	160.370us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	325.826us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			823	830	99.16

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	12	75.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.50	96.18	92.00	98.06	96.80	95.70	100.00	98.60	90.87

Failure Buckets

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:
- Test spi_host_smoke has 1 failures.
  - 20.spi_host_smoke.101185289406750152636065567960327842379632520139129524599533991591857466941267
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 145093983129 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6b057494) == 0x0
  UVM_INFO @ 145093983129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 22.spi_host_status_stall.90408189000611269993931825437960181820368034993995416202769288250010363807671
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 120386946425 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb84ebcd4) == 0x0
  UVM_INFO @ 120386946425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 1 failures.
  - 30.spi_host_stress_all.67706047186209595421911436938767334650357702965467549125357057263080004771509
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 22736067445 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb74c7ad4) == 0x0
  UVM_INFO @ 22736067445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
- Test spi_host_status_stall has 1 failures.
  - 48.spi_host_status_stall.47788973505574487009638848714797252570298869102245941977051888221677148646307
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 136785769188 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2319b214) == 0x0
  UVM_INFO @ 136785769188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 1 failures.
  - 49.spi_host_smoke.14368389943301452401997350276709310305598332012362156626001758334607820047935
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 81152281982 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x406b6254) == 0x0
  UVM_INFO @ 81152281982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 32.spi_host_stress_all.22292413786855589567162558832084950428088563110511843396205792899689998533248
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10002776189 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8e4cb114) == 0x0
  UVM_INFO @ 10002776189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 42.spi_host_spien.43351448642566097363887321790945789084530264488702164406856226263282916655833
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 23746732654 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfa124854) == 0x1
  UVM_INFO @ 23746732654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `be3d980075`