SPI_HOST Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.383m	13.720ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	29.201us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	7.000s	42.102us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	311.209us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	32.135us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	8.000s	124.159us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	7.000s	42.102us	20	20	100.00
		spi_host_csr_aliasing	2.000s	32.135us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	40.704us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	28.261us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	4.000s	155.533us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.567m	17.760ms	50	50	100.00
		spi_host_error_cmd	3.000s	101.641us	50	50	100.00
		spi_host_event	27.433m	40.741ms	50	50	100.00
V2	clock_rate	spi_host_speed	4.600m	6.160ms	49	50	98.00
V2	speed	spi_host_speed	4.600m	6.160ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	4.600m	6.160ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	7.533m	27.539ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	341.507us	50	50	100.00
V2	cpol_cpha	spi_host_speed	4.600m	6.160ms	49	50	98.00
V2	full_cycle	spi_host_speed	4.600m	6.160ms	49	50	98.00
V2	duplex	spi_host_smoke	10.383m	13.720ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	10.383m	13.720ms	49	50	98.00
V2	stress_all	spi_host_stress_all	3.717m	14.323ms	48	50	96.00
V2	spien	spi_host_spien	7.417m	39.122ms	50	50	100.00
V2	stall	spi_host_status_stall	9.367m	13.484ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	38.000s	1.595ms	48	50	96.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	17.441us	50	50	100.00
V2	intr_test	spi_host_intr_test	8.000s	61.535us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	136.451us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	136.451us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	29.201us	5	5	100.00
		spi_host_csr_rw	7.000s	42.102us	20	20	100.00
		spi_host_csr_aliasing	2.000s	32.135us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	75.658us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	29.201us	5	5	100.00
		spi_host_csr_rw	7.000s	42.102us	20	20	100.00
		spi_host_csr_aliasing	2.000s	32.135us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	75.658us	20	20	100.00
V2		TOTAL			682	690	98.84
V2S	tl_intg_err	spi_host_tl_intg_err	8.000s	177.610us	20	20	100.00
		spi_host_sec_cm	2.000s	107.046us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	8.000s	177.610us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			821	830	98.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	11	68.75
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.49	96.18	92.00	98.06	96.71	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
- Test spi_host_idlecsbactive has 2 failures.
  - 15.spi_host_idlecsbactive.100452544336835869338775474795123332929041982838628145517455491859596066960942
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10039117682 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5aa8c214) == 0x0
  UVM_INFO @ 10039117682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.spi_host_idlecsbactive.43226579920796977627994062800506354585295954839371759560657215482662094412902
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10093216973 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xeb326354) == 0x0
  UVM_INFO @ 10093216973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 1 failures.
  - 28.spi_host_stress_all.2656448560578932291160357322114142282364796817503228496549341351804412303188
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 16942798584 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa3cb7954) == 0x0
  UVM_INFO @ 16942798584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_speed has 1 failures.
  - 33.spi_host_speed.100324489736007251795620220840760799471258781940029535773808796590677638272611
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_speed/latest/run.log
```
  UVM_FATAL @ 78826364313 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3852ac94) == 0x0
  UVM_INFO @ 78826364313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 3 failures:
- Test spi_host_status_stall has 3 failures.
  - 13.spi_host_status_stall.86670410434430403431434022393604113586561512514629551359431537563226757318290
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 43139058873 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd9227854) == 0x1
  UVM_INFO @ 43139058873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.spi_host_status_stall.88563570798981203720499580911972822466088579440968287508486044671881222945469
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 41364595654 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7dc20414) == 0x1
  UVM_INFO @ 41364595654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 5.spi_host_smoke.64769367893504775614228222669111889891138377587280570071585890890840295997932
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 64348978186 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2a2393d4) == 0x0
  UVM_INFO @ 64348978186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 40.spi_host_stress_all.30469855544064667612940743421711222385920036482260445004969472538053445205820
    Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10007345699 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2be2add4) == 0x0
  UVM_INFO @ 10007345699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `1579f6a912`