SPI_HOST Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 9.467m 51.879ms 49 50 98.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 25.328us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 23.023us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 233.753us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 67.587us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 40.614us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 23.023us 20 20 100.00
spi_host_csr_aliasing 3.000s 67.587us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 17.689us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 69.313us 5 5 100.00
V1 TOTAL 114 115 99.13
V2 performance spi_host_performance 8.000s 32.204us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.500m 17.920ms 50 50 100.00
spi_host_error_cmd 12.000s 18.464us 50 50 100.00
spi_host_event 18.183m 145.839ms 50 50 100.00
V2 clock_rate spi_host_speed 4.833m 6.543ms 50 50 100.00
V2 speed spi_host_speed 4.833m 6.543ms 50 50 100.00
V2 chip_select_timing spi_host_speed 4.833m 6.543ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 6.400m 21.080ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 12.000s 720.959us 50 50 100.00
V2 cpol_cpha spi_host_speed 4.833m 6.543ms 50 50 100.00
V2 full_cycle spi_host_speed 4.833m 6.543ms 50 50 100.00
V2 duplex spi_host_smoke 9.467m 51.879ms 49 50 98.00
V2 tx_rx_only spi_host_smoke 9.467m 51.879ms 49 50 98.00
V2 stress_all spi_host_stress_all 3.600m 26.002ms 49 50 98.00
V2 spien spi_host_spien 6.300m 9.186ms 50 50 100.00
V2 stall spi_host_status_stall 9.617m 39.252ms 50 50 100.00
V2 Idlecsbactive spi_host_idlecsbactive 37.000s 6.963ms 50 50 100.00
V2 data_fifo_status data_fifo_status 0 0 --
V2 alert_test spi_host_alert_test 12.000s 44.239us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 40.918us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 97.890us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 97.890us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 25.328us 5 5 100.00
spi_host_csr_rw 3.000s 23.023us 20 20 100.00
spi_host_csr_aliasing 3.000s 67.587us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 31.770us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 25.328us 5 5 100.00
spi_host_csr_rw 3.000s 23.023us 20 20 100.00
spi_host_csr_aliasing 3.000s 67.587us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 31.770us 20 20 100.00
V2 TOTAL 689 690 99.86
V2S tl_intg_err spi_host_tl_intg_err 4.000s 82.769us 20 20 100.00
spi_host_sec_cm 7.000s 76.279us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 82.769us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 828 830 99.76

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 15 14 87.50
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.49 96.20 92.00 98.06 96.71 95.70 100.00 98.60 90.46

Failure Buckets

Past Results