0e5093d709| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 9.633m | 74.486ms | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 17.814us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 17.683us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 866.128us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 76.865us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 31.741us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 17.683us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 76.865us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 42.091us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 85.311us | 5 | 5 | 100.00 |
| V1 | TOTAL | 113 | 115 | 98.26 | |||
| V2 | performance | spi_host_performance | 8.000s | 108.868us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.783m | 15.471ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 7.000s | 70.404us | 50 | 50 | 100.00 | ||
| spi_host_event | 22.650m | 35.383ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 5.500m | 7.258ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 5.500m | 7.258ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 5.500m | 7.258ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 6.450m | 30.490ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 8.000s | 143.218us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 5.500m | 7.258ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 5.500m | 7.258ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 9.633m | 74.486ms | 48 | 50 | 96.00 |
| V2 | tx_rx_only | spi_host_smoke | 9.633m | 74.486ms | 48 | 50 | 96.00 |
| V2 | stress_all | spi_host_stress_all | 3.800m | 10.739ms | 48 | 50 | 96.00 |
| V2 | spien | spi_host_spien | 6.800m | 34.814ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 8.733m | 12.544ms | 48 | 50 | 96.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 40.000s | 2.485ms | 50 | 50 | 100.00 |
| V2 | data_fifo_status | data_fifo_status | 0 | 0 | -- | ||
| V2 | alert_test | spi_host_alert_test | 7.000s | 46.594us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 20.506us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 427.382us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 427.382us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 17.814us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 17.683us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 76.865us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 44.757us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 17.814us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 17.683us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 76.865us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 44.757us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 686 | 690 | 99.42 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 13.000s | 99.145us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 248.304us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 13.000s | 99.145us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 824 | 830 | 99.28 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 15 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 96.52 | 96.20 | 92.00 | 98.06 | 96.89 | 95.70 | 100.00 | 98.60 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:
Test spi_host_status_stall has 2 failures.
8.spi_host_status_stall.32262965274757519453504562586947873731190097521807534002793086168753061231913
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_status_stall/latest/run.log
UVM_FATAL @ 159927067560 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc2f04514) == 0x0
UVM_INFO @ 159927067560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.spi_host_status_stall.108925152307800080172838621458457642951564081092349984914309123994209177104873
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_status_stall/latest/run.log
UVM_FATAL @ 75307399373 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x68e12d4) == 0x0
UVM_INFO @ 75307399373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 2 failures.
10.spi_host_smoke.6594647339545868012100689112577205246674218071920952982965255684651055608411
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
UVM_FATAL @ 195127322939 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xfc1cb594) == 0x0
UVM_INFO @ 195127322939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_host_smoke.44625213071360885586004071172429889611766048088608373643389175469447164964720
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_smoke/latest/run.log
UVM_FATAL @ 160725351040 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb1f48554) == 0x0
UVM_INFO @ 160725351040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
26.spi_host_stress_all.83435973810201120356833198738612232685197643595536873815612658833022058950684
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_stress_all/latest/run.log
UVM_FATAL @ 20485352424 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xae1f5314) == 0x0
UVM_INFO @ 20485352424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
39.spi_host_stress_all.34375640499271321292597167790394541200538293338956693538715712900875984228079
Line 317, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10739381189 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9cf97854) == 0x0
UVM_INFO @ 10739381189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---