8cb25a6867
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_host_smoke | 9.017m | 22.294ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | spi_host_csr_hw_reset | 4.000s | 47.427us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_host_csr_rw | 4.000s | 66.714us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 219.993us | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_host_csr_aliasing | 4.000s | 22.867us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 67.502us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 4.000s | 66.714us | 20 | 20 | 100.00 |
spi_host_csr_aliasing | 4.000s | 22.867us | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_host_mem_walk | 4.000s | 35.214us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 35.128us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | performance | spi_host_performance | 4.000s | 29.761us | 50 | 50 | 100.00 |
V2 | error_event_intr | spi_host_overflow_underflow | 3.583m | 19.566ms | 50 | 50 | 100.00 |
spi_host_error_cmd | 3.000s | 29.373us | 50 | 50 | 100.00 | ||
spi_host_event | 22.950m | 36.108ms | 50 | 50 | 100.00 | ||
V2 | clock_rate | spi_host_speed | 5.883m | 29.218ms | 50 | 50 | 100.00 |
V2 | speed | spi_host_speed | 5.883m | 29.218ms | 50 | 50 | 100.00 |
V2 | chip_select_timing | spi_host_speed | 5.883m | 29.218ms | 50 | 50 | 100.00 |
V2 | sw_reset | spi_host_sw_reset | 3.533m | 18.303ms | 50 | 50 | 100.00 |
V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 205.298us | 50 | 50 | 100.00 |
V2 | cpol_cpha | spi_host_speed | 5.883m | 29.218ms | 50 | 50 | 100.00 |
V2 | full_cycle | spi_host_speed | 5.883m | 29.218ms | 50 | 50 | 100.00 |
V2 | duplex | spi_host_smoke | 9.017m | 22.294ms | 50 | 50 | 100.00 |
V2 | tx_rx_only | spi_host_smoke | 9.017m | 22.294ms | 50 | 50 | 100.00 |
V2 | stress_all | spi_host_stress_all | 2.983m | 11.548ms | 48 | 50 | 96.00 |
V2 | spien | spi_host_spien | 7.083m | 33.997ms | 50 | 50 | 100.00 |
V2 | stall | spi_host_status_stall | 9.917m | 95.910ms | 48 | 50 | 96.00 |
V2 | Idlecsbactive | spi_host_idlecsbactive | 41.000s | 6.261ms | 49 | 50 | 98.00 |
V2 | data_fifo_status | data_fifo_status | 0 | 0 | -- | ||
V2 | alert_test | spi_host_alert_test | 3.000s | 17.140us | 50 | 50 | 100.00 |
V2 | intr_test | spi_host_intr_test | 4.000s | 18.353us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 210.713us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 210.713us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 4.000s | 47.427us | 5 | 5 | 100.00 |
spi_host_csr_rw | 4.000s | 66.714us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 4.000s | 22.867us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 4.000s | 60.831us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_host_csr_hw_reset | 4.000s | 47.427us | 5 | 5 | 100.00 |
spi_host_csr_rw | 4.000s | 66.714us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 4.000s | 22.867us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 4.000s | 60.831us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 685 | 690 | 99.28 | |||
V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 52.050us | 20 | 20 | 100.00 |
spi_host_sec_cm | 3.000s | 67.310us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 52.050us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | winbond | winbond | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 825 | 830 | 99.40 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 16 | 15 | 12 | 75.00 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 2 | 0 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
96.50 | 96.20 | 92.00 | 98.06 | 96.71 | 95.70 | 100.00 | 98.60 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 4 failures:
Test spi_host_stress_all has 2 failures.
6.spi_host_stress_all.54451831837153551159733677031285170585840998067385345897892723874289212088056
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_stress_all/latest/run.log
UVM_FATAL @ 13038599640 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbd715e54) == 0x0
UVM_INFO @ 13038599640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_host_stress_all.111895427371852295707960941414209228111572876108659903861621387774156511786104
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_stress_all/latest/run.log
UVM_FATAL @ 24949609056 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc26ccb54) == 0x0
UVM_INFO @ 24949609056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
27.spi_host_status_stall.88134549333389918305081836200723338141735414119228769282161479251874451522332
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_status_stall/latest/run.log
UVM_FATAL @ 133471156380 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x48b05794) == 0x0
UVM_INFO @ 133471156380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_idlecsbactive has 1 failures.
35.spi_host_idlecsbactive.108454558940668992886955500913794433882281555978214991663625759678320591685545
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10076225682 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xdf530d14) == 0x0
UVM_INFO @ 10076225682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == *
has 1 failures:
28.spi_host_status_stall.79228972747181714352837987141744522678038270147035164459604353071829536359783
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_status_stall/latest/run.log
UVM_FATAL @ 23767589580 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc646f514) == 0x1
UVM_INFO @ 23767589580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---