SPI_HOST Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.167m 135.808ms 48 50 96.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 48.054us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 69.201us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 566.532us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 2.000s 18.690us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 4.000s 49.737us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 69.201us 20 20 100.00
spi_host_csr_aliasing 2.000s 18.690us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 15.114us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 35.847us 5 5 100.00
V1 TOTAL 113 115 98.26
V2 performance spi_host_performance 3.000s 91.564us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.600m 38.958ms 49 50 98.00
spi_host_error_cmd 3.000s 33.482us 50 50 100.00
spi_host_event 21.583m 60.653ms 50 50 100.00
V2 clock_rate spi_host_speed 6.267m 52.130ms 50 50 100.00
V2 speed spi_host_speed 6.267m 52.130ms 50 50 100.00
V2 chip_select_timing spi_host_speed 6.267m 52.130ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 3.683m 13.522ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 3.000s 554.932us 50 50 100.00
V2 cpol_cpha spi_host_speed 6.267m 52.130ms 50 50 100.00
V2 full_cycle spi_host_speed 6.267m 52.130ms 50 50 100.00
V2 duplex spi_host_smoke 10.167m 135.808ms 48 50 96.00
V2 tx_rx_only spi_host_smoke 10.167m 135.808ms 48 50 96.00
V2 stress_all spi_host_stress_all 3.900m 10.002ms 46 50 92.00
V2 spien spi_host_spien 7.017m 34.028ms 50 50 100.00
V2 stall spi_host_status_stall 9.650m 189.056ms 45 50 90.00
V2 Idlecsbactive spi_host_idlecsbactive 44.000s 13.458ms 49 50 98.00
V2 data_fifo_status data_fifo_status 0 0 --
V2 alert_test spi_host_alert_test 2.000s 23.398us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 34.933us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 122.623us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 122.623us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 48.054us 5 5 100.00
spi_host_csr_rw 3.000s 69.201us 20 20 100.00
spi_host_csr_aliasing 2.000s 18.690us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 126.083us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 48.054us 5 5 100.00
spi_host_csr_rw 3.000s 69.201us 20 20 100.00
spi_host_csr_aliasing 2.000s 18.690us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 126.083us 20 20 100.00
V2 TOTAL 679 690 98.41
V2S tl_intg_err spi_host_tl_intg_err 4.000s 89.581us 20 20 100.00
spi_host_sec_cm 3.000s 479.165us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 89.581us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 817 830 98.43

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 15 11 68.75
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.51 96.20 92.00 98.06 96.80 95.70 100.00 98.60 90.87

Failure Buckets

Past Results