01a208901a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 10.167m | 135.808ms | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 48.054us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 69.201us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 566.532us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 2.000s | 18.690us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 49.737us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 69.201us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 2.000s | 18.690us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 15.114us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 35.847us | 5 | 5 | 100.00 |
| V1 | TOTAL | 113 | 115 | 98.26 | |||
| V2 | performance | spi_host_performance | 3.000s | 91.564us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.600m | 38.958ms | 49 | 50 | 98.00 |
| spi_host_error_cmd | 3.000s | 33.482us | 50 | 50 | 100.00 | ||
| spi_host_event | 21.583m | 60.653ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 6.267m | 52.130ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 6.267m | 52.130ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 6.267m | 52.130ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 3.683m | 13.522ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 3.000s | 554.932us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 6.267m | 52.130ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 6.267m | 52.130ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 10.167m | 135.808ms | 48 | 50 | 96.00 |
| V2 | tx_rx_only | spi_host_smoke | 10.167m | 135.808ms | 48 | 50 | 96.00 |
| V2 | stress_all | spi_host_stress_all | 3.900m | 10.002ms | 46 | 50 | 92.00 |
| V2 | spien | spi_host_spien | 7.017m | 34.028ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 9.650m | 189.056ms | 45 | 50 | 90.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 44.000s | 13.458ms | 49 | 50 | 98.00 |
| V2 | data_fifo_status | data_fifo_status | 0 | 0 | -- | ||
| V2 | alert_test | spi_host_alert_test | 2.000s | 23.398us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 34.933us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 122.623us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 122.623us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 48.054us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 69.201us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 2.000s | 18.690us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 126.083us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 48.054us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 69.201us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 2.000s | 18.690us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 126.083us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 679 | 690 | 98.41 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 89.581us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 479.165us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 89.581us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 817 | 830 | 98.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 15 | 11 | 68.75 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 96.51 | 96.20 | 92.00 | 98.06 | 96.80 | 95.70 | 100.00 | 98.60 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:
Test spi_host_status_stall has 3 failures.
3.spi_host_status_stall.41710616233003966043804096637409411507782683560196206348470004749215528954866
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log
UVM_FATAL @ 69225585856 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x14c02314) == 0x0
UVM_INFO @ 69225585856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_host_status_stall.100325079193688046411063077659463900214386434354061636564023401956695228321014
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
UVM_FATAL @ 80112118810 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x66115c14) == 0x0
UVM_INFO @ 80112118810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_smoke has 1 failures.
38.spi_host_smoke.42877949929108617990730354516106998313124129295181446675722442165768160089168
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_smoke/latest/run.log
UVM_FATAL @ 120682097089 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2b112714) == 0x0
UVM_INFO @ 120682097089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_idlecsbactive has 1 failures.
41.spi_host_idlecsbactive.32282301796292470876891080392589473385816355446812252600412166385744529930160
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10094400776 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2966c414) == 0x0
UVM_INFO @ 10094400776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
Test spi_host_smoke has 1 failures.
5.spi_host_smoke.4201334769987650874719923677828264649890584352700378471926352104117429022414
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log
UVM_FATAL @ 107821314832 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x28de7394) == 0x0
UVM_INFO @ 107821314832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 2 failures.
13.spi_host_stress_all.111751514873420246820871793093882455350437213874701625383452603723517412946786
Line 317, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15573901081 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd452c994) == 0x0
UVM_INFO @ 15573901081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.spi_host_stress_all.57775738035397511189230275467502065388632864966184523503742731238952378469305
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_stress_all/latest/run.log
UVM_FATAL @ 23120548486 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x48b85dd4) == 0x0
UVM_INFO @ 23120548486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_overflow_underflow has 1 failures.
16.spi_host_overflow_underflow.47197304672426424858537648059435602937653205254912944376713907646045042072134
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 38958023904 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa128e194) == 0x0
UVM_INFO @ 38958023904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:
21.spi_host_stress_all.80550491299234257556702170243482231071997761194741045829781762872331034547360
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10001782184 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5ff45394) == 0x0
UVM_INFO @ 10001782184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.spi_host_stress_all.68582814198647448263753338952946030522559398362412298727444507354405466178285
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_stress_all/latest/run.log
UVM_FATAL @ 12394924587 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc8b72454) == 0x0
UVM_INFO @ 12394924587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: * has 1 failures:
29.spi_host_status_stall.84284658831703671901451500421923701023324543582557599384143812863498906036272
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
UVM_ERROR @ 2932815194 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0
UVM_INFO @ 2932815194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
36.spi_host_status_stall.113842835636488756994916720866726077056683014523205696006216493178922153485315
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_status_stall/latest/run.log
UVM_FATAL @ 22200852804 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xaa20b114) == 0x1
UVM_INFO @ 22200852804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---