SPI_HOST Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.450m	60.317ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	72.372us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	7.000s	34.699us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	8.000s	164.186us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	8.000s	30.194us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	13.000s	36.904us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	7.000s	34.699us	20	20	100.00
		spi_host_csr_aliasing	8.000s	30.194us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	14.890us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	18.270us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	3.000s	30.181us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.583m	6.353ms	50	50	100.00
		spi_host_error_cmd	3.000s	17.444us	50	50	100.00
		spi_host_event	15.150m	93.126ms	50	50	100.00
V2	clock_rate	spi_host_speed	3.683m	15.815ms	50	50	100.00
V2	speed	spi_host_speed	3.683m	15.815ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	3.683m	15.815ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	5.600m	11.977ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	211.815us	50	50	100.00
V2	cpol_cpha	spi_host_speed	3.683m	15.815ms	50	50	100.00
V2	full_cycle	spi_host_speed	3.683m	15.815ms	50	50	100.00
V2	duplex	spi_host_smoke	10.450m	60.317ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	10.450m	60.317ms	49	50	98.00
V2	stress_all	spi_host_stress_all	4.433m	18.426ms	50	50	100.00
V2	spien	spi_host_spien	5.150m	7.025ms	50	50	100.00
V2	stall	spi_host_status_stall	9.483m	13.473ms	44	50	88.00
V2	Idlecsbactive	spi_host_idlecsbactive	46.000s	1.578ms	50	50	100.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	51.186us	50	50	100.00
V2	intr_test	spi_host_intr_test	8.000s	16.398us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	14.000s	907.486us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	14.000s	907.486us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	72.372us	5	5	100.00
		spi_host_csr_rw	7.000s	34.699us	20	20	100.00
		spi_host_csr_aliasing	8.000s	30.194us	5	5	100.00
		spi_host_same_csr_outstanding	7.000s	69.821us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	72.372us	5	5	100.00
		spi_host_csr_rw	7.000s	34.699us	20	20	100.00
		spi_host_csr_aliasing	8.000s	30.194us	5	5	100.00
		spi_host_same_csr_outstanding	7.000s	69.821us	20	20	100.00
V2		TOTAL			684	690	99.13
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	690.789us	20	20	100.00
		spi_host_sec_cm	3.000s	214.059us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	690.789us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			823	830	99.16

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	14	87.50
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.48	96.20	92.00	98.06	96.54	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
- Test spi_host_status_stall has 2 failures.
  - 2.spi_host_status_stall.72525126651895165695792529435981926663410883063866260552499175596272078831210
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 12818751812 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8a0c75d4) == 0x1
  UVM_INFO @ 12818751812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.spi_host_status_stall.112980555990224624839202415939153314724134249948277564788738481002508998541127
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 43247014081 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x40e21314) == 0x1
  UVM_INFO @ 43247014081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
- Test spi_host_smoke has 1 failures.
  - 10.spi_host_smoke.26069803110438408467417852172363762625790301245976804148768122063047739042075
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 117266241717 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xca91ee54) == 0x0
  UVM_INFO @ 117266241717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 48.spi_host_status_stall.98012853100602860198229515215391081316641332803794609275372795276461800155510
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 136776414883 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xea52ca14) == 0x0
  UVM_INFO @ 136776414883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 12.spi_host_status_stall.3456896294149685467751391117231239706644731832800730140018807427657854756397
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log
```
  UVM_ERROR @ 1190263526 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0
  UVM_INFO @ 1190263526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 14.spi_host_status_stall.108568013360351421591480221554796470643356834569109916762779761412752100270629
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 61553468988 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xfce6a054) == 0x0
  UVM_INFO @ 61553468988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 37.spi_host_status_stall.110836434687291962862094256691071484851280437475336453755796066320902056107398
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 25662157971 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2947cf54) == 0x1
  UVM_INFO @ 25662157971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a182fcef27`