SPI_HOST Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	11.317m	54.268ms	47	50	94.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	19.460us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	44.382us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	259.904us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	236.410us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	85.531us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	44.382us	20	20	100.00
		spi_host_csr_aliasing	3.000s	236.410us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	40.324us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	43.341us	5	5	100.00
V1		TOTAL			112	115	97.39
V2	performance	spi_host_performance	3.000s	111.359us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.167m	34.458ms	49	50	98.00
		spi_host_error_cmd	3.000s	18.730us	50	50	100.00
		spi_host_event	24.183m	65.324ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.367m	7.188ms	50	50	100.00
V2	speed	spi_host_speed	5.367m	7.188ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.367m	7.188ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	5.400m	11.758ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	1.256ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.367m	7.188ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.367m	7.188ms	50	50	100.00
V2	duplex	spi_host_smoke	11.317m	54.268ms	47	50	94.00
V2	tx_rx_only	spi_host_smoke	11.317m	54.268ms	47	50	94.00
V2	stress_all	spi_host_stress_all	4.633m	17.841ms	46	50	92.00
V2	spien	spi_host_spien	6.350m	14.811ms	50	50	100.00
V2	stall	spi_host_status_stall	8.967m	22.760ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	47.000s	6.427ms	50	50	100.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	16.472us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	221.674us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	96.818us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	96.818us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	19.460us	5	5	100.00
		spi_host_csr_rw	3.000s	44.382us	20	20	100.00
		spi_host_csr_aliasing	3.000s	236.410us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	38.421us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	19.460us	5	5	100.00
		spi_host_csr_rw	3.000s	44.382us	20	20	100.00
		spi_host_csr_aliasing	3.000s	236.410us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	38.421us	20	20	100.00
V2		TOTAL			682	690	98.84
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	86.445us	20	20	100.00
		spi_host_sec_cm	2.000s	47.162us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	86.445us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			819	830	98.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	12	75.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.51	96.20	92.00	98.06	96.80	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 6 failures:
- Test spi_host_smoke has 1 failures.
  - 0.spi_host_smoke.55369837741552278437896587689352725704346858751851191500557854405682121639794
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 78792342246 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1fd51a94) == 0x0
  UVM_INFO @ 78792342246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 2 failures.
  - 11.spi_host_status_stall.51016957632009493760651960949032571756802978164253165670813886766575317531033
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 106755900310 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc54d4794) == 0x0
  UVM_INFO @ 106755900310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.spi_host_status_stall.25576686672591229112668489131765500582481541017557067842407906131633507471405
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 36378923348 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6bd924d4) == 0x0
  UVM_INFO @ 36378923348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 2 failures.
  - 20.spi_host_stress_all.90862285511274619981161459523958377299378360643762808520795724642766310495920
    Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 15866857103 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7cc17454) == 0x0
  UVM_INFO @ 15866857103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.spi_host_stress_all.111431806034278794557723361957070855459717716448782679099854189074291030261552
    Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 18150773974 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2f6bc814) == 0x0
  UVM_INFO @ 18150773974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_overflow_underflow has 1 failures.
  - 30.spi_host_overflow_underflow.67103980214701446429676919032919845878666378315934492405027913594912543196314
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 45252344887 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x573535d4) == 0x0
  UVM_INFO @ 45252344887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:
- Test spi_host_stress_all has 1 failures.
  - 21.spi_host_stress_all.41918788494324872162722194682601504643678205807436656585681062304221063388359
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 22815047934 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x35d22414) == 0x0
  UVM_INFO @ 22815047934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 2 failures.
  - 32.spi_host_smoke.78348524842702545357014446151500506975105914328244660764596057274519045721089
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 112878006560 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4fb24514) == 0x0
  UVM_INFO @ 112878006560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.spi_host_smoke.108030750182840062331263017102998175055855297909870148330003283021778639155233
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 153758970079 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6431c4d4) == 0x0
  UVM_INFO @ 153758970079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 13.spi_host_status_stall.38732811218950331764467734557732046631139791363479081227960835713437851762426
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 15651553062 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x29a62594) == 0x1
  UVM_INFO @ 15651553062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 23.spi_host_stress_all.109748314517831502265333097319762344693099599875501453749479768351632143131647
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10000931906 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd063ecd4) == 0x0
  UVM_INFO @ 10000931906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `b29ffbb03c`