SPI_HOST Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	11.317m	186.022ms	46	50	92.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	43.870us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	23.822us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	636.070us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	94.736us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	161.343us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	23.822us	20	20	100.00
		spi_host_csr_aliasing	3.000s	94.736us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	44.256us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	16.884us	5	5	100.00
V1		TOTAL			111	115	96.52
V2	performance	spi_host_performance	7.000s	105.211us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.833m	3.418ms	50	50	100.00
		spi_host_error_cmd	3.000s	20.275us	50	50	100.00
		spi_host_event	19.033m	530.684ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.267m	27.018ms	50	50	100.00
V2	speed	spi_host_speed	5.267m	27.018ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.267m	27.018ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	5.533m	11.759ms	49	50	98.00
V2	passthrough_mode	spi_host_passthrough_mode	8.000s	347.088us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.267m	27.018ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.267m	27.018ms	50	50	100.00
V2	duplex	spi_host_smoke	11.317m	186.022ms	46	50	92.00
V2	tx_rx_only	spi_host_smoke	11.317m	186.022ms	46	50	92.00
V2	stress_all	spi_host_stress_all	5.200m	11.512ms	48	50	96.00
V2	spien	spi_host_spien	6.983m	30.649ms	50	50	100.00
V2	stall	spi_host_status_stall	9.067m	43.606ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	41.000s	2.742ms	49	50	98.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	58.608us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	17.346us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	66.399us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	66.399us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	43.870us	5	5	100.00
		spi_host_csr_rw	3.000s	23.822us	20	20	100.00
		spi_host_csr_aliasing	3.000s	94.736us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	26.317us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	43.870us	5	5	100.00
		spi_host_csr_rw	3.000s	23.822us	20	20	100.00
		spi_host_csr_aliasing	3.000s	94.736us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	26.317us	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	91.814us	20	20	100.00
		spi_host_sec_cm	3.000s	97.128us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	91.814us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			819	830	98.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	11	68.75
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.45	96.20	92.00	98.06	96.45	95.70	100.00	98.60	90.46

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 6 failures:
- Test spi_host_smoke has 4 failures.
  - 5.spi_host_smoke.57888552433368373052314409426943606659043495494625941938517122932078213400994
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 104920506002 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x38d270d4) == 0x0
  UVM_INFO @ 104920506002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.spi_host_smoke.2419365182542193198431679056956867753542206226145657912199256445801254655496
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 186022499497 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x46f40b14) == 0x0
  UVM_INFO @ 186022499497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test spi_host_status_stall has 1 failures.
  - 22.spi_host_status_stall.14323421411157421440467909176796228355686467162419000831714823728503003905153
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 94482958246 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xfec52194) == 0x0
  UVM_INFO @ 94482958246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_idlecsbactive has 1 failures.
  - 43.spi_host_idlecsbactive.82716987454440904380061648436816051073658052866696729284157996144550071412520
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10064651320 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5cd34094) == 0x0
  UVM_INFO @ 10064651320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:
- Test spi_host_stress_all has 1 failures.
  - 2.spi_host_stress_all.38081958589466771858727961006064031510475683585464064009903095599588850774001
    Line 317, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 11512196129 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x653abf94) == 0x0
  UVM_INFO @ 11512196129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_sw_reset has 1 failures.
  - 35.spi_host_sw_reset.64983847539947189187767061505853199315468633999505953774082793502515673066083
    Line 324, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 10076015083 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc6ff19d4) == 0x0
  UVM_INFO @ 10076015083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 9.spi_host_status_stall.43768400514261733755395487861077785708612565093693994849201888838662867548525
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 13222149098 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc29a0a94) == 0x1
  UVM_INFO @ 13222149098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 21.spi_host_status_stall.79206088245763341841356501337082980633415186894060271534750477712921021833236
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 62774310796 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x27e0a594) == 0x0
  UVM_INFO @ 62774310796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 29.spi_host_stress_all.29578786058096018848282177540488100800781127690715912548704904259974927984571
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 23031558508 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x774152d4) == 0x0
  UVM_INFO @ 23031558508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `32d52b8d41`