302b24f3c6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 10.217m | 90.116ms | 47 | 50 | 94.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 17.597us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 26.656us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 1.666ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 20.709us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 189.512us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 26.656us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 20.709us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 24.167us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 21.902us | 5 | 5 | 100.00 |
| V1 | TOTAL | 112 | 115 | 97.39 | |||
| V2 | performance | spi_host_performance | 3.000s | 210.753us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.983m | 7.623ms | 49 | 50 | 98.00 |
| spi_host_error_cmd | 3.000s | 18.394us | 50 | 50 | 100.00 | ||
| spi_host_event | 18.317m | 106.341ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 6.583m | 17.347ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 6.583m | 17.347ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 6.583m | 17.347ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 9.517m | 19.531ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 3.000s | 2.075ms | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 6.583m | 17.347ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 6.583m | 17.347ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 10.217m | 90.116ms | 47 | 50 | 94.00 |
| V2 | tx_rx_only | spi_host_smoke | 10.217m | 90.116ms | 47 | 50 | 94.00 |
| V2 | stress_all | spi_host_stress_all | 3.650m | 24.539ms | 47 | 50 | 94.00 |
| V2 | spien | spi_host_spien | 7.667m | 37.819ms | 49 | 50 | 98.00 |
| V2 | stall | spi_host_status_stall | 10.000m | 13.343ms | 47 | 50 | 94.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 43.000s | 1.636ms | 50 | 50 | 100.00 |
| V2 | data_fifo_status | data_fifo_status | 0 | 0 | -- | ||
| V2 | alert_test | spi_host_alert_test | 3.000s | 15.329us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 27.598us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 43.885us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 43.885us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 17.597us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 26.656us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 20.709us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 22.263us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 17.597us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 26.656us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 20.709us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 22.263us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 682 | 690 | 98.84 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 75.631us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 44.173us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 75.631us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 819 | 830 | 98.67 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 15 | 11 | 68.75 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 96.49 | 96.20 | 92.00 | 98.07 | 96.63 | 95.70 | 100.00 | 98.60 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 6 failures:
Test spi_host_stress_all has 3 failures.
2.spi_host_stress_all.113117346773838725901109809655399790956068257683008550370239836301273168715276
Line 297, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/latest/run.log
UVM_FATAL @ 17834305368 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1eaf4154) == 0x0
UVM_INFO @ 17834305368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_host_stress_all.5196742480537539773268776613551243660490950212693237263501418400250892186100
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10047885940 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa8d31954) == 0x0
UVM_INFO @ 10047885940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_smoke has 1 failures.
10.spi_host_smoke.75640680867366960284259214113772053428054808562423189745977226987989415483090
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
UVM_FATAL @ 107813778290 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7d1cd9d4) == 0x0
UVM_INFO @ 107813778290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
30.spi_host_status_stall.48112827962673749568216522007966713478963357168589214865448332757310006581467
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_status_stall/latest/run.log
UVM_FATAL @ 182579635337 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2bc1eb14) == 0x0
UVM_INFO @ 182579635337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_overflow_underflow has 1 failures.
33.spi_host_overflow_underflow.17985083089206156147761769790496770489314226845830426657996087014151735474531
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 48803687977 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcb9ad414) == 0x0
UVM_INFO @ 48803687977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
Test spi_host_spien has 1 failures.
11.spi_host_spien.35903443093790880009582097487616513291952140731767400154248163495313646451552
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_spien/latest/run.log
UVM_FATAL @ 34262786384 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xafc21954) == 0x1
UVM_INFO @ 34262786384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
43.spi_host_status_stall.77342500297811791685164465461479812372517935127829493811706643340783596719213
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10832294204 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1845f394) == 0x1
UVM_INFO @ 10832294204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
6.spi_host_status_stall.12434517285219345092071362602379423370370245694136892686687552039223988432602
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_status_stall/latest/run.log
UVM_FATAL @ 20629079968 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe2375654) == 0x1
UVM_INFO @ 20629079968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
24.spi_host_smoke.48954628905609424689957745197378114219359809491070641472846091907407753886818
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_smoke/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
45.spi_host_smoke.97356642700324711632900904158190301612999233368873857380904146596962248827157
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_smoke/latest/run.log
UVM_FATAL @ 72405633748 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe825fb14) == 0x0
UVM_INFO @ 72405633748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---