f92a5ee77b
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_host_smoke | 10.250m | 22.346ms | 47 | 50 | 94.00 |
V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 59.663us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_host_csr_rw | 9.000s | 42.571us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_host_csr_bit_bash | 9.000s | 200.108us | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_host_csr_aliasing | 8.000s | 59.010us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 9.000s | 95.126us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 9.000s | 42.571us | 20 | 20 | 100.00 |
spi_host_csr_aliasing | 8.000s | 59.010us | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_host_mem_walk | 14.000s | 37.338us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_host_mem_partial_access | 13.000s | 38.148us | 5 | 5 | 100.00 |
V1 | TOTAL | 112 | 115 | 97.39 | |||
V2 | performance | spi_host_performance | 3.000s | 109.876us | 50 | 50 | 100.00 |
V2 | error_event_intr | spi_host_overflow_underflow | 4.017m | 20.584ms | 49 | 50 | 98.00 |
spi_host_error_cmd | 3.000s | 19.668us | 50 | 50 | 100.00 | ||
spi_host_event | 18.917m | 143.842ms | 50 | 50 | 100.00 | ||
V2 | clock_rate | spi_host_speed | 6.650m | 30.510ms | 50 | 50 | 100.00 |
V2 | speed | spi_host_speed | 6.650m | 30.510ms | 50 | 50 | 100.00 |
V2 | chip_select_timing | spi_host_speed | 6.650m | 30.510ms | 50 | 50 | 100.00 |
V2 | sw_reset | spi_host_sw_reset | 4.500m | 8.725ms | 50 | 50 | 100.00 |
V2 | passthrough_mode | spi_host_passthrough_mode | 3.000s | 317.425us | 50 | 50 | 100.00 |
V2 | cpol_cpha | spi_host_speed | 6.650m | 30.510ms | 50 | 50 | 100.00 |
V2 | full_cycle | spi_host_speed | 6.650m | 30.510ms | 50 | 50 | 100.00 |
V2 | duplex | spi_host_smoke | 10.250m | 22.346ms | 47 | 50 | 94.00 |
V2 | tx_rx_only | spi_host_smoke | 10.250m | 22.346ms | 47 | 50 | 94.00 |
V2 | stress_all | spi_host_stress_all | 4.667m | 20.015ms | 47 | 50 | 94.00 |
V2 | spien | spi_host_spien | 6.533m | 16.858ms | 50 | 50 | 100.00 |
V2 | stall | spi_host_status_stall | 9.367m | 25.864ms | 44 | 50 | 88.00 |
V2 | Idlecsbactive | spi_host_idlecsbactive | 38.000s | 5.609ms | 50 | 50 | 100.00 |
V2 | data_fifo_status | data_fifo_status | 0 | 0 | -- | ||
V2 | alert_test | spi_host_alert_test | 3.000s | 16.179us | 50 | 50 | 100.00 |
V2 | intr_test | spi_host_intr_test | 18.000s | 40.844us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_host_tl_errors | 18.000s | 29.182us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_host_tl_errors | 18.000s | 29.182us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 59.663us | 5 | 5 | 100.00 |
spi_host_csr_rw | 9.000s | 42.571us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 8.000s | 59.010us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 22.000s | 88.124us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 59.663us | 5 | 5 | 100.00 |
spi_host_csr_rw | 9.000s | 42.571us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 8.000s | 59.010us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 22.000s | 88.124us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 680 | 690 | 98.55 | |||
V2S | tl_intg_err | spi_host_tl_intg_err | 19.000s | 1.302ms | 20 | 20 | 100.00 |
spi_host_sec_cm | 2.000s | 70.608us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 19.000s | 1.302ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | winbond | winbond | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 817 | 830 | 98.43 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 7 | 87.50 |
V2 | 16 | 15 | 12 | 75.00 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 2 | 0 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
96.49 | 96.20 | 92.00 | 98.07 | 96.63 | 95.70 | 100.00 | 98.60 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 7 failures:
Test spi_host_overflow_underflow has 1 failures.
1.spi_host_overflow_underflow.46924370358221573495336694387583854166680173749739874024704337845901426098506
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 59678403577 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9b76f754) == 0x0
UVM_INFO @ 59678403577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 2 failures.
21.spi_host_smoke.61226908704190560402565434572312381082369255414862042086748337221080791420659
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_smoke/latest/run.log
UVM_FATAL @ 84046675555 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc57d8fd4) == 0x0
UVM_INFO @ 84046675555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.spi_host_smoke.52062701540594116574420804951831955199653819517562418813305532196621183430419
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_smoke/latest/run.log
UVM_FATAL @ 66237646094 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf6adf954) == 0x0
UVM_INFO @ 66237646094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 2 failures.
29.spi_host_status_stall.88881416145545426842875557749637370867451434582750422830792264859811645462236
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
UVM_FATAL @ 126109653569 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4cb511d4) == 0x0
UVM_INFO @ 126109653569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.spi_host_status_stall.10494034370314384695486954561650230889050983265491161661670683857984466107469
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_status_stall/latest/run.log
UVM_FATAL @ 157793531686 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2bc8f214) == 0x0
UVM_INFO @ 157793531686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 2 failures.
31.spi_host_stress_all.53258533479704603364833530130678575584207136004791988173089882434400104112357
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10037002322 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x36041cd4) == 0x0
UVM_INFO @ 10037002322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.spi_host_stress_all.8446887431705391751076845006555660073271938293319785702889021918191750720749
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_stress_all/latest/run.log
UVM_FATAL @ 21009385780 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x390973d4) == 0x0
UVM_INFO @ 21009385780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 3 failures:
Test spi_host_status_stall has 2 failures.
9.spi_host_status_stall.16973196998030940581258073690112385046497515158815066707743780815551439073763
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log
UVM_FATAL @ 25457312048 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3db39014) == 0x0
UVM_INFO @ 25457312048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_host_status_stall.60783725708165506245415425093041450911870256951337285545046030914233016866856
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_status_stall/latest/run.log
UVM_FATAL @ 50370646721 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x552e6ad4) == 0x0
UVM_INFO @ 50370646721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
32.spi_host_smoke.100035482928913506169035567649540459169421868116117504723459137664509046814373
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_smoke/latest/run.log
UVM_FATAL @ 114976241135 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd0cab154) == 0x0
UVM_INFO @ 114976241135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == *
has 1 failures:
10.spi_host_stress_all.82554506222181991662653391440038909782864516688764002367940826970905384834884
Line 299, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_stress_all/latest/run.log
UVM_FATAL @ 11172106870 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe6dbe854) == 0x0
UVM_INFO @ 11172106870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == *
has 1 failures:
41.spi_host_status_stall.53403252735664176596829647063104433281789611922733726011978779017000783682016
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
UVM_FATAL @ 12218481393 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb1097494) == 0x1
UVM_INFO @ 12218481393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: *
has 1 failures:
45.spi_host_status_stall.37719252175379838993542492766850460284145906128299180071706046105836160860978
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_status_stall/latest/run.log
UVM_ERROR @ 1673644295 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0
UVM_INFO @ 1673644295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---