a8c9c17a8c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 10.717m | 54.111ms | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 7.000s | 23.441us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 7.000s | 21.718us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 9.000s | 467.817us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 16.344us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 13.000s | 104.918us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 7.000s | 21.718us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 16.344us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 7.000s | 29.648us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 4.000s | 19.716us | 5 | 5 | 100.00 |
| V1 | TOTAL | 113 | 115 | 98.26 | |||
| V2 | performance | spi_host_performance | 8.000s | 33.108us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.400m | 11.077ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 12.000s | 23.728us | 50 | 50 | 100.00 | ||
| spi_host_event | 23.750m | 31.495ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 5.767m | 49.378ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 5.767m | 49.378ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 5.767m | 49.378ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 7.833m | 14.560ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 12.000s | 207.559us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 5.767m | 49.378ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 5.767m | 49.378ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 10.717m | 54.111ms | 48 | 50 | 96.00 |
| V2 | tx_rx_only | spi_host_smoke | 10.717m | 54.111ms | 48 | 50 | 96.00 |
| V2 | stress_all | spi_host_stress_all | 4.317m | 25.024ms | 50 | 50 | 100.00 |
| V2 | spien | spi_host_spien | 6.633m | 15.643ms | 48 | 50 | 96.00 |
| V2 | stall | spi_host_status_stall | 8.450m | 11.984ms | 50 | 50 | 100.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 47.000s | 6.264ms | 50 | 50 | 100.00 |
| V2 | data_fifo_status | data_fifo_status | 0 | 0 | -- | ||
| V2 | alert_test | spi_host_alert_test | 12.000s | 15.150us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 8.000s | 18.590us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 10.000s | 160.531us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 10.000s | 160.531us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 7.000s | 23.441us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 21.718us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 16.344us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 12.000s | 61.141us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 7.000s | 23.441us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 21.718us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 16.344us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 12.000s | 61.141us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 688 | 690 | 99.71 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 9.000s | 184.684us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 207.779us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 9.000s | 184.684us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 826 | 830 | 99.52 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 15 | 14 | 87.50 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 96.53 | 96.21 | 92.04 | 98.06 | 96.93 | 95.70 | 100.00 | 98.60 | 90.87 |
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
16.spi_host_smoke.106285343545345637155915296955567700537408260256416977413474204578577868950548
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_smoke/latest/run.log
UVM_FATAL @ 107065853898 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf93d9514) == 0x0
UVM_INFO @ 107065853898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
21.spi_host_spien.70655097368405852755701138375128905048926120217193980595486906037170666522087
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_spien/latest/run.log
UVM_FATAL @ 10009906146 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xffc0b714) == 0x0
UVM_INFO @ 10009906146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
31.spi_host_smoke.6082989504050287782930225235453360844628043708832072253514572601907176504477
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_smoke/latest/run.log
UVM_FATAL @ 87966990683 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc0bccbd4) == 0x0
UVM_INFO @ 87966990683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
47.spi_host_spien.107533632964439320438780365565116813775676860350706910475123645329744377235919
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_spien/latest/run.log
UVM_FATAL @ 10021197761 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf2c43e14) == 0x0
UVM_INFO @ 10021197761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---