dd5ad5fb77| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 10.733m | 28.758ms | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 49.702us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 19.958us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 4.000s | 125.135us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 20.446us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 43.436us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 19.958us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 20.446us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 106.692us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 30.967us | 5 | 5 | 100.00 |
| V1 | TOTAL | 113 | 115 | 98.26 | |||
| V2 | performance | spi_host_performance | 4.000s | 342.106us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.417m | 16.427ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 7.000s | 27.700us | 50 | 50 | 100.00 | ||
| spi_host_event | 18.150m | 258.589ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 5.567m | 75.299ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 5.567m | 75.299ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 5.567m | 75.299ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 6.417m | 11.712ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 7.000s | 505.313us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 5.567m | 75.299ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 5.567m | 75.299ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 10.733m | 28.758ms | 48 | 50 | 96.00 |
| V2 | tx_rx_only | spi_host_smoke | 10.733m | 28.758ms | 48 | 50 | 96.00 |
| V2 | stress_all | spi_host_stress_all | 3.983m | 9.214ms | 50 | 50 | 100.00 |
| V2 | spien | spi_host_spien | 8.900m | 71.267ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 9.467m | 13.043ms | 49 | 50 | 98.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 48.000s | 1.754ms | 49 | 50 | 98.00 |
| V2 | data_fifo_status | data_fifo_status | 0 | 0 | -- | ||
| V2 | alert_test | spi_host_alert_test | 7.000s | 24.027us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 16.459us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 450.978us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 450.978us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 49.702us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 19.958us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 20.446us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 26.915us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 49.702us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 19.958us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 20.446us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 26.915us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 688 | 690 | 99.71 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 250.795us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 2.000s | 244.210us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 250.795us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 826 | 830 | 99.52 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 15 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 96.52 | 96.21 | 92.04 | 98.06 | 96.84 | 95.70 | 100.00 | 98.60 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:
Test spi_host_smoke has 2 failures.
14.spi_host_smoke.65133785381010581885404682754355965469621932052275238895514681091245632752018
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_smoke/latest/run.log
UVM_FATAL @ 76919166780 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5f25f854) == 0x0
UVM_INFO @ 76919166780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.spi_host_smoke.80615814028947629711043694458260981064738977882515100038122408729639400577912
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_smoke/latest/run.log
UVM_FATAL @ 98903433464 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8ccf0f54) == 0x0
UVM_INFO @ 98903433464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
24.spi_host_status_stall.97953962974900673017704774856886515356138002719430025613193328574029954534849
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_status_stall/latest/run.log
UVM_FATAL @ 53029203787 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2fe98614) == 0x0
UVM_INFO @ 53029203787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
25.spi_host_idlecsbactive.106836380821743489488326085547790407203758270286194037836611308436314340815927
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10072642675 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa9ffb214) == 0x0
UVM_INFO @ 10072642675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---