SPI_HOST Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.083m 26.967ms 49 50 98.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 54.468us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 35.254us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 159.082us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 2.000s 87.098us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 91.021us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 35.254us 20 20 100.00
spi_host_csr_aliasing 2.000s 87.098us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 17.245us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 46.425us 5 5 100.00
V1 TOTAL 114 115 99.13
V2 performance spi_host_performance 4.000s 463.426us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.017m 15.196ms 50 50 100.00
spi_host_error_cmd 3.000s 20.136us 50 50 100.00
spi_host_event 18.400m 121.598ms 50 50 100.00
V2 clock_rate spi_host_speed 5.983m 7.486ms 50 50 100.00
V2 speed spi_host_speed 5.983m 7.486ms 50 50 100.00
V2 chip_select_timing spi_host_speed 5.983m 7.486ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 2.750m 8.961ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 3.000s 221.909us 50 50 100.00
V2 cpol_cpha spi_host_speed 5.983m 7.486ms 50 50 100.00
V2 full_cycle spi_host_speed 5.983m 7.486ms 50 50 100.00
V2 duplex spi_host_smoke 10.083m 26.967ms 49 50 98.00
V2 tx_rx_only spi_host_smoke 10.083m 26.967ms 49 50 98.00
V2 stress_all spi_host_stress_all 3.817m 18.700ms 50 50 100.00
V2 spien spi_host_spien 7.983m 10.728ms 49 50 98.00
V2 stall spi_host_status_stall 9.617m 13.168ms 49 50 98.00
V2 Idlecsbactive spi_host_idlecsbactive 55.000s 8.965ms 49 50 98.00
V2 data_fifo_status data_fifo_status 0 0 --
V2 alert_test spi_host_alert_test 3.000s 36.981us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 17.235us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 96.384us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 96.384us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 54.468us 5 5 100.00
spi_host_csr_rw 3.000s 35.254us 20 20 100.00
spi_host_csr_aliasing 2.000s 87.098us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 55.649us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 54.468us 5 5 100.00
spi_host_csr_rw 3.000s 35.254us 20 20 100.00
spi_host_csr_aliasing 2.000s 87.098us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 55.649us 20 20 100.00
V2 TOTAL 687 690 99.57
V2S tl_intg_err spi_host_tl_intg_err 4.000s 74.403us 20 20 100.00
spi_host_sec_cm 3.000s 78.433us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 74.403us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 826 830 99.52

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 15 12 75.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.52 96.21 92.04 98.06 96.84 95.70 100.00 98.60 90.87

Failure Buckets

Past Results