SPI_HOST Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 9.017m 12.169ms 49 50 98.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 72.109us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 35.579us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 69.502us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 8.000s 50.719us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 8.000s 56.541us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 35.579us 20 20 100.00
spi_host_csr_aliasing 8.000s 50.719us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 17.672us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 18.617us 5 5 100.00
V1 TOTAL 114 115 99.13
V2 performance spi_host_performance 5.000s 33.439us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.350m 6.400ms 50 50 100.00
spi_host_error_cmd 7.000s 21.256us 50 50 100.00
spi_host_event 19.783m 28.299ms 50 50 100.00
V2 clock_rate spi_host_speed 5.733m 28.076ms 50 50 100.00
V2 speed spi_host_speed 5.733m 28.076ms 50 50 100.00
V2 chip_select_timing spi_host_speed 5.733m 28.076ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 6.200m 12.300ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 10.000s 653.765us 50 50 100.00
V2 cpol_cpha spi_host_speed 5.733m 28.076ms 50 50 100.00
V2 full_cycle spi_host_speed 5.733m 28.076ms 50 50 100.00
V2 duplex spi_host_smoke 9.017m 12.169ms 49 50 98.00
V2 tx_rx_only spi_host_smoke 9.017m 12.169ms 49 50 98.00
V2 stress_all spi_host_stress_all 2.983m 11.383ms 50 50 100.00
V2 spien spi_host_spien 6.417m 29.040ms 49 50 98.00
V2 stall spi_host_status_stall 10.167m 13.870ms 50 50 100.00
V2 Idlecsbactive spi_host_idlecsbactive 52.000s 17.053ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.350m 6.400ms 50 50 100.00
V2 alert_test spi_host_alert_test 4.000s 15.516us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 19.602us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 130.847us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 130.847us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 72.109us 5 5 100.00
spi_host_csr_rw 3.000s 35.579us 20 20 100.00
spi_host_csr_aliasing 8.000s 50.719us 5 5 100.00
spi_host_same_csr_outstanding 8.000s 61.735us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 72.109us 5 5 100.00
spi_host_csr_rw 3.000s 35.579us 20 20 100.00
spi_host_csr_aliasing 8.000s 50.719us 5 5 100.00
spi_host_same_csr_outstanding 8.000s 61.735us 20 20 100.00
V2 TOTAL 689 690 99.86
V2S tl_intg_err spi_host_tl_intg_err 5.000s 110.511us 20 20 100.00
spi_host_sec_cm 3.000s 41.985us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 5.000s 110.511us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 828 830 99.76

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 15 15 14 93.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.55 96.23 92.07 98.07 96.96 95.70 100.00 98.60 90.87

Failure Buckets

Past Results