SPI_HOST Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 9.900m 25.074ms 48 50 96.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 64.752us 5 5 100.00
V1 csr_rw spi_host_csr_rw 8.000s 21.561us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 612.246us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 2.000s 42.543us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 4.000s 26.595us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 8.000s 21.561us 20 20 100.00
spi_host_csr_aliasing 2.000s 42.543us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 43.967us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 21.350us 5 5 100.00
V1 TOTAL 113 115 98.26
V2 performance spi_host_performance 9.000s 212.112us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.333m 15.433ms 49 50 98.00
spi_host_error_cmd 7.000s 45.736us 50 50 100.00
spi_host_event 19.133m 63.407ms 50 50 100.00
V2 clock_rate spi_host_speed 6.700m 34.460ms 50 50 100.00
V2 speed spi_host_speed 6.700m 34.460ms 50 50 100.00
V2 chip_select_timing spi_host_speed 6.700m 34.460ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 6.850m 25.106ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 10.000s 250.721us 50 50 100.00
V2 cpol_cpha spi_host_speed 6.700m 34.460ms 50 50 100.00
V2 full_cycle spi_host_speed 6.700m 34.460ms 50 50 100.00
V2 duplex spi_host_smoke 9.900m 25.074ms 48 50 96.00
V2 tx_rx_only spi_host_smoke 9.900m 25.074ms 48 50 96.00
V2 stress_all spi_host_stress_all 4.333m 10.984ms 49 50 98.00
V2 spien spi_host_spien 6.250m 18.404ms 50 50 100.00
V2 stall spi_host_status_stall 10.467m 48.699ms 45 50 90.00
V2 Idlecsbactive spi_host_idlecsbactive 40.000s 5.488ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 3.333m 15.433ms 49 50 98.00
V2 alert_test spi_host_alert_test 7.000s 179.319us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 88.039us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 549.452us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 549.452us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 64.752us 5 5 100.00
spi_host_csr_rw 8.000s 21.561us 20 20 100.00
spi_host_csr_aliasing 2.000s 42.543us 5 5 100.00
spi_host_same_csr_outstanding 4.000s 49.362us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 64.752us 5 5 100.00
spi_host_csr_rw 8.000s 21.561us 20 20 100.00
spi_host_csr_aliasing 2.000s 42.543us 5 5 100.00
spi_host_same_csr_outstanding 4.000s 49.362us 20 20 100.00
V2 TOTAL 682 690 98.84
V2S tl_intg_err spi_host_tl_intg_err 4.000s 174.471us 20 20 100.00
spi_host_sec_cm 5.000s 142.528us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 174.471us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 820 830 98.80

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 15 15 11 73.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.51 96.23 92.07 98.07 96.79 95.70 100.00 98.60 90.46

Failure Buckets

Past Results