SPI_HOST Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: `8fdb25c8d9`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.900m	25.074ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	64.752us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	8.000s	21.561us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	612.246us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	42.543us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	26.595us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	8.000s	21.561us	20	20	100.00
		spi_host_csr_aliasing	2.000s	42.543us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	43.967us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	21.350us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	9.000s	212.112us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.333m	15.433ms	49	50	98.00
		spi_host_error_cmd	7.000s	45.736us	50	50	100.00
		spi_host_event	19.133m	63.407ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.700m	34.460ms	50	50	100.00
V2	speed	spi_host_speed	6.700m	34.460ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.700m	34.460ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	6.850m	25.106ms	49	50	98.00
V2	passthrough_mode	spi_host_passthrough_mode	10.000s	250.721us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.700m	34.460ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.700m	34.460ms	50	50	100.00
V2	duplex	spi_host_smoke	9.900m	25.074ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	9.900m	25.074ms	48	50	96.00
V2	stress_all	spi_host_stress_all	4.333m	10.984ms	49	50	98.00
V2	spien	spi_host_spien	6.250m	18.404ms	50	50	100.00
V2	stall	spi_host_status_stall	10.467m	48.699ms	45	50	90.00
V2	Idlecsbactive	spi_host_idlecsbactive	40.000s	5.488ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.333m	15.433ms	49	50	98.00
V2	alert_test	spi_host_alert_test	7.000s	179.319us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	88.039us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	549.452us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	549.452us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	64.752us	5	5	100.00
		spi_host_csr_rw	8.000s	21.561us	20	20	100.00
		spi_host_csr_aliasing	2.000s	42.543us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	49.362us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	64.752us	5	5	100.00
		spi_host_csr_rw	8.000s	21.561us	20	20	100.00
		spi_host_csr_aliasing	2.000s	42.543us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	49.362us	20	20	100.00
V2		TOTAL			682	690	98.84
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	174.471us	20	20	100.00
		spi_host_sec_cm	5.000s	142.528us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	174.471us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			820	830	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.51	96.23	92.07	98.07	96.79	95.70	100.00	98.60	90.46

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 9 failures:
- Test spi_host_status_stall has 4 failures.
  - 0.spi_host_status_stall.26953473274872754061462612899758156732221264251349420571857002438817536367453
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 102031048172 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb47bf554) == 0x0
  UVM_INFO @ 102031048172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.spi_host_status_stall.79975055798555707558788157072179673375073420549266252458994457554216957494362
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 45652912059 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd64aeb54) == 0x0
  UVM_INFO @ 45652912059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test spi_host_stress_all has 1 failures.
  - 5.spi_host_stress_all.103484995675029381887718150464944267584915335051568854635453152540435985784165
    Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 35227272625 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5848354) == 0x0
  UVM_INFO @ 35227272625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 2 failures.
  - 26.spi_host_smoke.17378541257748975693415645610990768251939747583944431743288582264786799578053
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 66257536889 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xfcbb1f54) == 0x0
  UVM_INFO @ 66257536889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.spi_host_smoke.30946580434988433536962453920535191567657979317071910907649386377057248650340
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 77351762988 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbaaa6354) == 0x0
  UVM_INFO @ 77351762988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_overflow_underflow has 1 failures.
  - 35.spi_host_overflow_underflow.99799627397028400565322217529103858110948014265934700815547556803367430628177
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 48333509779 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf2733ed4) == 0x0
  UVM_INFO @ 48333509779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_sw_reset has 1 failures.
  - 49.spi_host_sw_reset.6721813685987552182983515210653328688365275221540041892637252092937035892986
    Line 301, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 25106365451 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2fd147d4) == 0x0
  UVM_INFO @ 25106365451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 4.spi_host_status_stall.68266633636719228153928184755532021915766083495910884927410785180090278465264
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 57879335356 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc6139bd4) == 0x0
  UVM_INFO @ 57879335356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8fdb25c8d9`