SPI_HOST Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 9.117m 21.802ms 48 50 96.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 25.438us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 18.544us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 4.000s 307.679us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 55.159us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 12.000s 145.123us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 18.544us 20 20 100.00
spi_host_csr_aliasing 3.000s 55.159us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 14.461us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 22.950us 5 5 100.00
V1 TOTAL 113 115 98.26
V2 performance spi_host_performance 9.000s 271.452us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.833m 18.037ms 49 50 98.00
spi_host_error_cmd 4.000s 19.990us 50 50 100.00
spi_host_event 21.583m 173.393ms 50 50 100.00
V2 clock_rate spi_host_speed 7.200m 9.170ms 50 50 100.00
V2 speed spi_host_speed 7.200m 9.170ms 50 50 100.00
V2 chip_select_timing spi_host_speed 7.200m 9.170ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 10.867m 59.681ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 7.000s 180.469us 50 50 100.00
V2 cpol_cpha spi_host_speed 7.200m 9.170ms 50 50 100.00
V2 full_cycle spi_host_speed 7.200m 9.170ms 50 50 100.00
V2 duplex spi_host_smoke 9.117m 21.802ms 48 50 96.00
V2 tx_rx_only spi_host_smoke 9.117m 21.802ms 48 50 96.00
V2 stress_all spi_host_stress_all 4.000m 16.625ms 49 50 98.00
V2 spien spi_host_spien 5.700m 29.941ms 50 50 100.00
V2 stall spi_host_status_stall 9.167m 26.122ms 49 50 98.00
V2 Idlecsbactive spi_host_idlecsbactive 39.000s 6.220ms 49 50 98.00
V2 data_fifo_status spi_host_overflow_underflow 2.833m 18.037ms 49 50 98.00
V2 alert_test spi_host_alert_test 7.000s 31.364us 50 50 100.00
V2 intr_test spi_host_intr_test 12.000s 42.093us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 150.255us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 150.255us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 25.438us 5 5 100.00
spi_host_csr_rw 3.000s 18.544us 20 20 100.00
spi_host_csr_aliasing 3.000s 55.159us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 21.775us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 25.438us 5 5 100.00
spi_host_csr_rw 3.000s 18.544us 20 20 100.00
spi_host_csr_aliasing 3.000s 55.159us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 21.775us 20 20 100.00
V2 TOTAL 685 690 99.28
V2S tl_intg_err spi_host_tl_intg_err 7.000s 188.072us 20 20 100.00
spi_host_sec_cm 3.000s 39.929us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 7.000s 188.072us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 823 830 99.16

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 15 15 10 66.67
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.54 96.23 92.07 98.07 96.88 95.70 100.00 98.60 90.87

Failure Buckets

Past Results