SPI_HOST Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: 6e698b4dfe

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.350m 51.296ms 49 50 98.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 95.377us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 37.766us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 4.000s 57.826us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 58.289us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 52.256us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 37.766us 20 20 100.00
spi_host_csr_aliasing 3.000s 58.289us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 16.466us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 22.393us 5 5 100.00
V1 TOTAL 114 115 99.13
V2 performance spi_host_performance 4.000s 103.091us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.267m 4.252ms 50 50 100.00
spi_host_error_cmd 14.000s 49.485us 50 50 100.00
spi_host_event 23.267m 148.163ms 50 50 100.00
V2 clock_rate spi_host_speed 5.950m 31.093ms 49 50 98.00
V2 speed spi_host_speed 5.950m 31.093ms 49 50 98.00
V2 chip_select_timing spi_host_speed 5.950m 31.093ms 49 50 98.00
V2 sw_reset spi_host_sw_reset 3.700m 17.456ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 456.499us 50 50 100.00
V2 cpol_cpha spi_host_speed 5.950m 31.093ms 49 50 98.00
V2 full_cycle spi_host_speed 5.950m 31.093ms 49 50 98.00
V2 duplex spi_host_smoke 10.350m 51.296ms 49 50 98.00
V2 tx_rx_only spi_host_smoke 10.350m 51.296ms 49 50 98.00
V2 stress_all spi_host_stress_all 4.317m 15.419ms 50 50 100.00
V2 spien spi_host_spien 5.450m 26.333ms 50 50 100.00
V2 stall spi_host_status_stall 9.567m 12.614ms 48 50 96.00
V2 Idlecsbactive spi_host_idlecsbactive 42.000s 15.372ms 49 50 98.00
V2 data_fifo_status spi_host_overflow_underflow 3.267m 4.252ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 38.936us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 50.160us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 4.000s 65.785us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 4.000s 65.785us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 95.377us 5 5 100.00
spi_host_csr_rw 3.000s 37.766us 20 20 100.00
spi_host_csr_aliasing 3.000s 58.289us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 104.041us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 95.377us 5 5 100.00
spi_host_csr_rw 3.000s 37.766us 20 20 100.00
spi_host_csr_aliasing 3.000s 58.289us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 104.041us 20 20 100.00
V2 TOTAL 686 690 99.42
V2S tl_intg_err spi_host_tl_intg_err 4.000s 73.677us 20 20 100.00
spi_host_sec_cm 4.000s 135.273us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 73.677us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 825 830 99.40

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.55 96.23 92.07 98.07 96.96 95.70 100.00 98.60 90.87

Failure Buckets

Past Results