SPI_HOST Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.867m 60.896ms 47 50 94.00
V1 csr_hw_reset spi_host_csr_hw_reset 8.000s 19.587us 5 5 100.00
V1 csr_rw spi_host_csr_rw 7.000s 25.044us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 19.000s 181.907us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 17.000s 54.647us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 8.000s 46.428us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 7.000s 25.044us 20 20 100.00
spi_host_csr_aliasing 17.000s 54.647us 5 5 100.00
V1 mem_walk spi_host_mem_walk 17.000s 90.718us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 12.000s 34.484us 5 5 100.00
V1 TOTAL 112 115 97.39
V2 performance spi_host_performance 13.000s 32.557us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.517m 20.701ms 50 50 100.00
spi_host_error_cmd 12.000s 22.198us 50 50 100.00
spi_host_event 18.933m 111.503ms 50 50 100.00
V2 clock_rate spi_host_speed 6.800m 17.238ms 50 50 100.00
V2 speed spi_host_speed 6.800m 17.238ms 50 50 100.00
V2 chip_select_timing spi_host_speed 6.800m 17.238ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 7.783m 31.692ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 18.000s 591.703us 50 50 100.00
V2 cpol_cpha spi_host_speed 6.800m 17.238ms 50 50 100.00
V2 full_cycle spi_host_speed 6.800m 17.238ms 50 50 100.00
V2 duplex spi_host_smoke 10.867m 60.896ms 47 50 94.00
V2 tx_rx_only spi_host_smoke 10.867m 60.896ms 47 50 94.00
V2 stress_all spi_host_stress_all 4.700m 5.936ms 48 50 96.00
V2 spien spi_host_spien 6.117m 15.607ms 49 50 98.00
V2 stall spi_host_status_stall 8.967m 46.875ms 48 50 96.00
V2 Idlecsbactive spi_host_idlecsbactive 40.000s 7.463ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 3.517m 20.701ms 50 50 100.00
V2 alert_test spi_host_alert_test 7.000s 23.163us 50 50 100.00
V2 intr_test spi_host_intr_test 12.000s 16.763us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 8.000s 185.154us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 8.000s 185.154us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 8.000s 19.587us 5 5 100.00
spi_host_csr_rw 7.000s 25.044us 20 20 100.00
spi_host_csr_aliasing 17.000s 54.647us 5 5 100.00
spi_host_same_csr_outstanding 8.000s 83.874us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 8.000s 19.587us 5 5 100.00
spi_host_csr_rw 7.000s 25.044us 20 20 100.00
spi_host_csr_aliasing 17.000s 54.647us 5 5 100.00
spi_host_same_csr_outstanding 8.000s 83.874us 20 20 100.00
V2 TOTAL 685 690 99.28
V2S tl_intg_err spi_host_tl_intg_err 18.000s 922.113us 20 20 100.00
spi_host_sec_cm 7.000s 152.319us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 18.000s 922.113us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 822 830 99.04

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.55 96.23 92.07 98.07 96.96 95.70 100.00 98.60 90.87

Failure Buckets

Past Results