be1c4a4f52| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 9.200m | 24.500ms | 47 | 50 | 94.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 28.742us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 21.473us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 58.076us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 18.929us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 20.414us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 21.473us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 18.929us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 17.582us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 32.397us | 5 | 5 | 100.00 |
| V1 | TOTAL | 112 | 115 | 97.39 | |||
| V2 | performance | spi_host_performance | 4.000s | 107.551us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.800m | 61.546ms | 48 | 50 | 96.00 |
| spi_host_error_cmd | 3.000s | 31.752us | 50 | 50 | 100.00 | ||
| spi_host_event | 19.133m | 269.483ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 4.450m | 6.423ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 4.450m | 6.423ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 4.450m | 6.423ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 12.667m | 47.549ms | 49 | 50 | 98.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 317.456us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 4.450m | 6.423ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 4.450m | 6.423ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 9.200m | 24.500ms | 47 | 50 | 94.00 |
| V2 | tx_rx_only | spi_host_smoke | 9.200m | 24.500ms | 47 | 50 | 94.00 |
| V2 | stress_all | spi_host_stress_all | 4.733m | 11.309ms | 49 | 50 | 98.00 |
| V2 | spien | spi_host_spien | 6.033m | 32.210ms | 49 | 50 | 98.00 |
| V2 | stall | spi_host_status_stall | 9.417m | 64.022ms | 47 | 50 | 94.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 37.000s | 5.028ms | 48 | 50 | 96.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 3.800m | 61.546ms | 48 | 50 | 96.00 |
| V2 | alert_test | spi_host_alert_test | 4.000s | 15.896us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 58.665us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 113.395us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 113.395us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 28.742us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 21.473us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 18.929us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 29.445us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 28.742us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 21.473us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 18.929us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 29.445us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 680 | 690 | 98.55 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 279.347us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 7.000s | 65.122us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 279.347us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 817 | 830 | 98.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 96.54 | 96.23 | 92.07 | 98.07 | 96.96 | 95.70 | 100.00 | 98.60 | 90.46 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 10 failures:
Test spi_host_idlecsbactive has 2 failures.
5.spi_host_idlecsbactive.19092906038707593471113329530251655341472524292699900204791883841377008231653
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10050084490 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x27561814) == 0x0
UVM_INFO @ 10050084490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_idlecsbactive.7361605355587579279117336950582365470737359053903101757428223852613281357882
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10044403433 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3f9aced4) == 0x0
UVM_INFO @ 10044403433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 1 failures.
7.spi_host_sw_reset.66412105266643306580353244004292387818928096632680338930443245974083240537910
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 47549398301 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb9202394) == 0x0
UVM_INFO @ 47549398301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 3 failures.
9.spi_host_status_stall.45788281912747755221632362192744619991023308004182169906080631099579836485175
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log
UVM_FATAL @ 60460819186 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7c4d2114) == 0x0
UVM_INFO @ 60460819186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_status_stall.54073704530385088404645696679210247511118076420982465559472190072852027844140
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
UVM_FATAL @ 88922870717 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x18c4bd4) == 0x0
UVM_INFO @ 88922870717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_overflow_underflow has 1 failures.
28.spi_host_overflow_underflow.98364391482185132466644862281073584656281309424959893481011154737125560665473
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 25293591432 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x61440854) == 0x0
UVM_INFO @ 25293591432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 3 failures.
37.spi_host_smoke.87947729334656568578414932558918263831223059068475769077056260975891039486815
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_smoke/latest/run.log
UVM_FATAL @ 130354176502 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcfa6ae54) == 0x0
UVM_INFO @ 130354176502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.spi_host_smoke.52694170007756016420066485051483911317160942652808237265170977888783619628996
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_smoke/latest/run.log
UVM_FATAL @ 152662925770 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2b8fa614) == 0x0
UVM_INFO @ 152662925770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
10.spi_host_stress_all.15292085579753900628616042548306282392319646450274922333200268572745323429649
Line 315, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10691562959 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd6b67a94) == 0x0
UVM_INFO @ 10691562959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
14.spi_host_overflow_underflow.81666144302743304320626953159798326934035671296588472247320529193011540898666
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 61545610457 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa2ee01d4) == 0x0
UVM_INFO @ 61545610457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
36.spi_host_spien.110427629924440884864085176454937143914947643135821749660904005233459076946103
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_spien/latest/run.log
UVM_FATAL @ 67057722969 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa7d64854) == 0x1
UVM_INFO @ 67057722969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---