SPI_HOST Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 9.200m 24.500ms 47 50 94.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 28.742us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 21.473us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 58.076us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 18.929us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 20.414us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 21.473us 20 20 100.00
spi_host_csr_aliasing 3.000s 18.929us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 17.582us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 32.397us 5 5 100.00
V1 TOTAL 112 115 97.39
V2 performance spi_host_performance 4.000s 107.551us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.800m 61.546ms 48 50 96.00
spi_host_error_cmd 3.000s 31.752us 50 50 100.00
spi_host_event 19.133m 269.483ms 50 50 100.00
V2 clock_rate spi_host_speed 4.450m 6.423ms 50 50 100.00
V2 speed spi_host_speed 4.450m 6.423ms 50 50 100.00
V2 chip_select_timing spi_host_speed 4.450m 6.423ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 12.667m 47.549ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 317.456us 50 50 100.00
V2 cpol_cpha spi_host_speed 4.450m 6.423ms 50 50 100.00
V2 full_cycle spi_host_speed 4.450m 6.423ms 50 50 100.00
V2 duplex spi_host_smoke 9.200m 24.500ms 47 50 94.00
V2 tx_rx_only spi_host_smoke 9.200m 24.500ms 47 50 94.00
V2 stress_all spi_host_stress_all 4.733m 11.309ms 49 50 98.00
V2 spien spi_host_spien 6.033m 32.210ms 49 50 98.00
V2 stall spi_host_status_stall 9.417m 64.022ms 47 50 94.00
V2 Idlecsbactive spi_host_idlecsbactive 37.000s 5.028ms 48 50 96.00
V2 data_fifo_status spi_host_overflow_underflow 3.800m 61.546ms 48 50 96.00
V2 alert_test spi_host_alert_test 4.000s 15.896us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 58.665us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 113.395us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 113.395us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 28.742us 5 5 100.00
spi_host_csr_rw 3.000s 21.473us 20 20 100.00
spi_host_csr_aliasing 3.000s 18.929us 5 5 100.00
spi_host_same_csr_outstanding 4.000s 29.445us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 28.742us 5 5 100.00
spi_host_csr_rw 3.000s 21.473us 20 20 100.00
spi_host_csr_aliasing 3.000s 18.929us 5 5 100.00
spi_host_same_csr_outstanding 4.000s 29.445us 20 20 100.00
V2 TOTAL 680 690 98.55
V2S tl_intg_err spi_host_tl_intg_err 4.000s 279.347us 20 20 100.00
spi_host_sec_cm 7.000s 65.122us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 279.347us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 817 830 98.43

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.54 96.23 92.07 98.07 96.96 95.70 100.00 98.60 90.46

Failure Buckets

Past Results