SPI_HOST Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	11.050m	167.382ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	19.971us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	18.401us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	814.567us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	45.239us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	108.129us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	18.401us	20	20	100.00
		spi_host_csr_aliasing	3.000s	45.239us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	18.066us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	55.285us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	4.000s	58.157us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.267m	53.638ms	49	50	98.00
		spi_host_error_cmd	3.000s	74.211us	50	50	100.00
		spi_host_event	16.467m	90.663ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.217m	108.123ms	50	50	100.00
V2	speed	spi_host_speed	6.217m	108.123ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.217m	108.123ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	10.767m	22.689ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	986.822us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.217m	108.123ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.217m	108.123ms	50	50	100.00
V2	duplex	spi_host_smoke	11.050m	167.382ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	11.050m	167.382ms	48	50	96.00
V2	stress_all	spi_host_stress_all	4.633m	13.840ms	49	50	98.00
V2	spien	spi_host_spien	6.233m	14.565ms	48	50	96.00
V2	stall	spi_host_status_stall	9.633m	176.377ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	43.000s	5.956ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.267m	53.638ms	49	50	98.00
V2	alert_test	spi_host_alert_test	3.000s	17.547us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	36.945us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	450.841us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	450.841us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	19.971us	5	5	100.00
		spi_host_csr_rw	3.000s	18.401us	20	20	100.00
		spi_host_csr_aliasing	3.000s	45.239us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	72.277us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	19.971us	5	5	100.00
		spi_host_csr_rw	3.000s	18.401us	20	20	100.00
		spi_host_csr_aliasing	3.000s	45.239us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	72.277us	20	20	100.00
V2		TOTAL			684	690	99.13
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	80.369us	20	20	100.00
		spi_host_sec_cm	3.000s	345.785us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	80.369us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			822	830	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.52	96.23	92.07	98.07	96.79	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 6 failures:
- Test spi_host_smoke has 2 failures.
  - 4.spi_host_smoke.87263999265767851122492888851279190885602152847169167549611667979149654606069
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 186985977088 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd558ad4) == 0x0
  UVM_INFO @ 186985977088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.spi_host_smoke.63719776892501560721481090431382174838458727485353604712363524212378418094406
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 167381681434 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x41e88cd4) == 0x0
  UVM_INFO @ 167381681434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 2 failures.
  - 8.spi_host_status_stall.79186989602880078362743293420649505702639312628806794981572680224941209551117
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 176376829866 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x36e22a94) == 0x0
  UVM_INFO @ 176376829866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.spi_host_status_stall.77421374233427060551805155982746130201529805377955987800623870844563112567729
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 101978856577 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcc8ebc14) == 0x0
  UVM_INFO @ 101978856577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 1 failures.
  - 45.spi_host_stress_all.47764608485907625279329608400468293524529020288271309476013325466316103434738
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 13069081467 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x688a5e54) == 0x0
  UVM_INFO @ 13069081467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_overflow_underflow has 1 failures.
  - 49.spi_host_overflow_underflow.50911406218444946864339525002258706537943141929162801705580567729924950709514
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 53638057745 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xaa72f654) == 0x0
  UVM_INFO @ 53638057745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
- Test spi_host_spien has 2 failures.
  - 6.spi_host_spien.97166672064565488343570444567837724629407843810499033883252937624587782152872
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 48921304023 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x94ea2794) == 0x1
  UVM_INFO @ 48921304023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.spi_host_spien.72446764071628898227516557453751033577313971789166402515307099603245129467915
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 17650088144 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc1c9e794) == 0x1
  UVM_INFO @ 17650088144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8db2a18db1`