3d5220a43f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 11.550m | 99.459ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 52.315us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 49.201us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 4.000s | 166.517us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 312.250us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 55.096us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 49.201us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 312.250us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 19.262us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 18.808us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | performance | spi_host_performance | 4.000s | 135.020us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.150m | 8.237ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 3.000s | 17.330us | 50 | 50 | 100.00 | ||
| spi_host_event | 24.950m | 220.381ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 5.083m | 6.587ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 5.083m | 6.587ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 5.083m | 6.587ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 6.600m | 13.883ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 146.718us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 5.083m | 6.587ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 5.083m | 6.587ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 11.550m | 99.459ms | 50 | 50 | 100.00 |
| V2 | tx_rx_only | spi_host_smoke | 11.550m | 99.459ms | 50 | 50 | 100.00 |
| V2 | stress_all | spi_host_stress_all | 3.900m | 30.195ms | 49 | 50 | 98.00 |
| V2 | spien | spi_host_spien | 6.517m | 29.819ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 9.400m | 20.224ms | 49 | 50 | 98.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 48.000s | 1.801ms | 49 | 50 | 98.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 3.150m | 8.237ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 3.000s | 21.182us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 22.595us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 89.128us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 89.128us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 52.315us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 49.201us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 312.250us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 27.967us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 52.315us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 49.201us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 312.250us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 27.967us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 687 | 690 | 99.57 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 95.341us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 390.770us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 95.341us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 827 | 830 | 99.64 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 15 | 15 | 12 | 80.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 96.54 | 96.23 | 92.07 | 98.07 | 96.88 | 95.70 | 100.00 | 98.60 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:
Test spi_host_idlecsbactive has 1 failures.
20.spi_host_idlecsbactive.107314625045257370762810965588944398686479099809796600555416445881531722259334
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10088332388 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x267c4d14) == 0x0
UVM_INFO @ 10088332388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
23.spi_host_status_stall.96513889562279957259058859384924172364859752909862381992970082541006048720656
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_status_stall/latest/run.log
UVM_FATAL @ 62880640833 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x98365a54) == 0x0
UVM_INFO @ 62880640833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
25.spi_host_stress_all.23754750629815115993167475133983834879488603562921260856571854572760976153764
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10058821012 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbaf72c54) == 0x0
UVM_INFO @ 10058821012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---