SPI_HOST Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 11.333m 62.560ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 7.000s 18.297us 5 5 100.00
V1 csr_rw spi_host_csr_rw 8.000s 39.907us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 6.000s 450.160us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 35.216us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 8.000s 24.749us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 8.000s 39.907us 20 20 100.00
spi_host_csr_aliasing 3.000s 35.216us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 41.135us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 19.243us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 3.000s 34.267us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.550m 16.194ms 50 50 100.00
spi_host_error_cmd 4.000s 113.186us 50 50 100.00
spi_host_event 21.450m 205.923ms 50 50 100.00
V2 clock_rate spi_host_speed 5.800m 22.668ms 50 50 100.00
V2 speed spi_host_speed 5.800m 22.668ms 50 50 100.00
V2 chip_select_timing spi_host_speed 5.800m 22.668ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 8.183m 35.291ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 3.000s 224.141us 50 50 100.00
V2 cpol_cpha spi_host_speed 5.800m 22.668ms 50 50 100.00
V2 full_cycle spi_host_speed 5.800m 22.668ms 50 50 100.00
V2 duplex spi_host_smoke 11.333m 62.560ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 11.333m 62.560ms 50 50 100.00
V2 stress_all spi_host_stress_all 4.250m 16.933ms 47 50 94.00
V2 spien spi_host_spien 6.300m 7.489ms 50 50 100.00
V2 stall spi_host_status_stall 11.117m 60.091ms 49 50 98.00
V2 Idlecsbactive spi_host_idlecsbactive 51.000s 6.909ms 49 50 98.00
V2 data_fifo_status spi_host_overflow_underflow 3.550m 16.194ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 23.700us 50 50 100.00
V2 intr_test spi_host_intr_test 8.000s 16.754us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 99.215us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 99.215us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 7.000s 18.297us 5 5 100.00
spi_host_csr_rw 8.000s 39.907us 20 20 100.00
spi_host_csr_aliasing 3.000s 35.216us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 179.979us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 7.000s 18.297us 5 5 100.00
spi_host_csr_rw 8.000s 39.907us 20 20 100.00
spi_host_csr_aliasing 3.000s 35.216us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 179.979us 20 20 100.00
V2 TOTAL 685 690 99.28
V2S tl_intg_err spi_host_tl_intg_err 8.000s 178.968us 20 20 100.00
spi_host_sec_cm 3.000s 67.048us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 8.000s 178.968us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 825 830 99.40

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.52 96.23 92.07 98.07 96.79 95.70 100.00 98.60 90.87

Failure Buckets

Past Results