SPI_HOST Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.150m	13.719ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	19.416us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	22.794us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	59.973us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	39.313us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	49.208us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	22.794us	20	20	100.00
		spi_host_csr_aliasing	2.000s	39.313us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	26.795us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	19.005us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	3.000s	110.733us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.100m	9.563ms	50	50	100.00
		spi_host_error_cmd	3.000s	17.728us	50	50	100.00
		spi_host_event	17.717m	52.728ms	50	50	100.00
V2	clock_rate	spi_host_speed	7.667m	12.556ms	50	50	100.00
V2	speed	spi_host_speed	7.667m	12.556ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	7.667m	12.556ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	7.817m	17.588ms	48	50	96.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	495.809us	50	50	100.00
V2	cpol_cpha	spi_host_speed	7.667m	12.556ms	50	50	100.00
V2	full_cycle	spi_host_speed	7.667m	12.556ms	50	50	100.00
V2	duplex	spi_host_smoke	10.150m	13.719ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	10.150m	13.719ms	50	50	100.00
V2	stress_all	spi_host_stress_all	4.917m	29.360ms	50	50	100.00
V2	spien	spi_host_spien	8.150m	19.865ms	50	50	100.00
V2	stall	spi_host_status_stall	9.367m	50.766ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	43.000s	3.150ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.100m	9.563ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	17.748us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	61.227us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	200.344us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	200.344us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	19.416us	5	5	100.00
		spi_host_csr_rw	3.000s	22.794us	20	20	100.00
		spi_host_csr_aliasing	2.000s	39.313us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	18.944us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	19.416us	5	5	100.00
		spi_host_csr_rw	3.000s	22.794us	20	20	100.00
		spi_host_csr_aliasing	2.000s	39.313us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	18.944us	20	20	100.00
V2		TOTAL			685	690	99.28
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	134.818us	20	20	100.00
		spi_host_sec_cm	3.000s	545.232us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	134.818us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			825	830	99.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	15	15	13	86.67
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.54	96.23	92.07	98.07	96.88	95.70	100.00	98.60	90.87

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:
  • Test spi_host_status_stall has 3 failures.

    • 17.spi_host_status_stall.80331226719556094596103734362936804933648132898634758557800302779612951909734
      Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 168882630758 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd9ac96d4) == 0x0
        UVM_INFO @ 168882630758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 28.spi_host_status_stall.26759964750438106416185173929853560658659878535468286619679886923488425631693
      Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 21376484600 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xccbc3d94) == 0x0
        UVM_INFO @ 21376484600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:
  • Test spi_host_sw_reset has 2 failures.

    • 42.spi_host_sw_reset.50093246789716677375230209068676784396197544039613636175080553162220017341314
      Line 282, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_sw_reset/latest/run.log

        UVM_FATAL @ 10797079858 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x852bef94) == 0x0
        UVM_INFO @ 10797079858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 44.spi_host_sw_reset.77372539686714202599511511014118849469409587528597383408040518975694566145709
      Line 303, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_sw_reset/latest/run.log

        UVM_FATAL @ 10058153721 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf62931d4) == 0x0
        UVM_INFO @ 10058153721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.06.28_12.03.39
• 2024.06.27_11.20.55
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