SPI_HOST Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.417m	167.932ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	17.873us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	12.000s	163.033us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	9.000s	216.653us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	12.000s	88.354us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	13.000s	64.360us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	12.000s	163.033us	20	20	100.00
		spi_host_csr_aliasing	12.000s	88.354us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	7.000s	46.312us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	17.000s	28.199us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	9.000s	32.814us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.200m	4.048ms	49	50	98.00
		spi_host_error_cmd	8.000s	26.565us	50	50	100.00
		spi_host_event	21.617m	351.699ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.667m	27.434ms	50	50	100.00
V2	speed	spi_host_speed	5.667m	27.434ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.667m	27.434ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	9.217m	38.470ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	2.537ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.667m	27.434ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.667m	27.434ms	50	50	100.00
V2	duplex	spi_host_smoke	9.417m	167.932ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	9.417m	167.932ms	48	50	96.00
V2	stress_all	spi_host_stress_all	3.283m	3.991ms	50	50	100.00
V2	spien	spi_host_spien	6.450m	49.480ms	50	50	100.00
V2	stall	spi_host_status_stall	9.650m	88.244ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	49.000s	13.930ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.200m	4.048ms	49	50	98.00
V2	alert_test	spi_host_alert_test	12.000s	97.297us	50	50	100.00
V2	intr_test	spi_host_intr_test	7.000s	58.483us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	9.000s	63.399us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	9.000s	63.399us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	17.873us	5	5	100.00
		spi_host_csr_rw	12.000s	163.033us	20	20	100.00
		spi_host_csr_aliasing	12.000s	88.354us	5	5	100.00
		spi_host_same_csr_outstanding	7.000s	42.716us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	17.873us	5	5	100.00
		spi_host_csr_rw	12.000s	163.033us	20	20	100.00
		spi_host_csr_aliasing	12.000s	88.354us	5	5	100.00
		spi_host_same_csr_outstanding	7.000s	42.716us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_tl_intg_err	12.000s	366.849us	20	20	100.00
		spi_host_sec_cm	2.000s	64.651us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	12.000s	366.849us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			824	830	99.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	13	86.67
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.00	90.92	83.18	92.77	89.69	95.70	100.00	95.07	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:
- Test spi_host_status_stall has 2 failures.
  - 15.spi_host_status_stall.21740578858480669183489322994792472829855058083044106713807714900106118689922
    Line 1180, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 103579511299 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5fe4b454) == 0x0
  UVM_INFO @ 103579511299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.spi_host_status_stall.39653608674253598120978450200169086207966985381865151960585271205370798755420
    Line 1098, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 70316560892 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xef28614) == 0x0
  UVM_INFO @ 70316560892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 2 failures.
  - 20.spi_host_smoke.112193968633062442875617536602033419118918751201991401519164643296443644142378
    Line 691, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 55357806565 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x892b1d94) == 0x0
  UVM_INFO @ 55357806565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.spi_host_smoke.110086804210025351488050804120785192241209465546973462458998116265459359370486
    Line 1039, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 167931891955 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb665e5d4) == 0x0
  UVM_INFO @ 167931891955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_overflow_underflow has 1 failures.
  - 48.spi_host_overflow_underflow.50564179980947181605194065450219175004554828837866550784006592085147380960773
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 46003599472 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf0ce58d4) == 0x0
  UVM_INFO @ 46003599472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 5.spi_host_status_stall.21161353106595278251403304315770017631797620641735562031471545135317395286486
    Line 1164, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 201373086211 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc17a6d14) == 0x0
  UVM_INFO @ 201373086211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eb56ef55d0`