e9ae10fb42
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_host_smoke | 8.817m | 12.112ms | 48 | 50 | 96.00 |
V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 18.680us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_host_csr_rw | 4.000s | 17.523us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 58.035us | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_host_csr_aliasing | 4.000s | 50.702us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 27.149us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 4.000s | 17.523us | 20 | 20 | 100.00 |
spi_host_csr_aliasing | 4.000s | 50.702us | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_host_mem_walk | 3.000s | 132.236us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 26.215us | 5 | 5 | 100.00 |
V1 | TOTAL | 113 | 115 | 98.26 | |||
V2 | performance | spi_host_performance | 3.000s | 34.071us | 50 | 50 | 100.00 |
V2 | error_event_intr | spi_host_overflow_underflow | 2.850m | 7.116ms | 50 | 50 | 100.00 |
spi_host_error_cmd | 3.000s | 51.829us | 50 | 50 | 100.00 | ||
spi_host_event | 22.417m | 65.564ms | 50 | 50 | 100.00 | ||
V2 | clock_rate | spi_host_speed | 4.533m | 17.754ms | 50 | 50 | 100.00 |
V2 | speed | spi_host_speed | 4.533m | 17.754ms | 50 | 50 | 100.00 |
V2 | chip_select_timing | spi_host_speed | 4.533m | 17.754ms | 50 | 50 | 100.00 |
V2 | sw_reset | spi_host_sw_reset | 3.100m | 6.488ms | 50 | 50 | 100.00 |
V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 1.158ms | 50 | 50 | 100.00 |
V2 | cpol_cpha | spi_host_speed | 4.533m | 17.754ms | 50 | 50 | 100.00 |
V2 | full_cycle | spi_host_speed | 4.533m | 17.754ms | 50 | 50 | 100.00 |
V2 | duplex | spi_host_smoke | 8.817m | 12.112ms | 48 | 50 | 96.00 |
V2 | tx_rx_only | spi_host_smoke | 8.817m | 12.112ms | 48 | 50 | 96.00 |
V2 | stress_all | spi_host_stress_all | 3.717m | 13.045ms | 48 | 50 | 96.00 |
V2 | spien | spi_host_spien | 6.767m | 32.548ms | 50 | 50 | 100.00 |
V2 | stall | spi_host_status_stall | 10.200m | 13.287ms | 47 | 50 | 94.00 |
V2 | Idlecsbactive | spi_host_idlecsbactive | 48.000s | 2.652ms | 50 | 50 | 100.00 |
V2 | data_fifo_status | spi_host_overflow_underflow | 2.850m | 7.116ms | 50 | 50 | 100.00 |
V2 | alert_test | spi_host_alert_test | 3.000s | 42.781us | 50 | 50 | 100.00 |
V2 | intr_test | spi_host_intr_test | 7.000s | 25.811us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_host_tl_errors | 9.000s | 53.040us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_host_tl_errors | 9.000s | 53.040us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 18.680us | 5 | 5 | 100.00 |
spi_host_csr_rw | 4.000s | 17.523us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 4.000s | 50.702us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 9.000s | 26.142us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 18.680us | 5 | 5 | 100.00 |
spi_host_csr_rw | 4.000s | 17.523us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 4.000s | 50.702us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 9.000s | 26.142us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 685 | 690 | 99.28 | |||
V2S | tl_intg_err | spi_host_tl_intg_err | 6.000s | 97.666us | 20 | 20 | 100.00 |
spi_host_sec_cm | 3.000s | 567.368us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 6.000s | 97.666us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | winbond | winbond | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 823 | 830 | 99.16 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 7 | 87.50 |
V2 | 15 | 15 | 13 | 86.67 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 2 | 0 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
91.00 | 90.92 | 83.18 | 92.77 | 89.69 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 3 failures:
Test spi_host_smoke has 1 failures.
4.spi_host_smoke.33419113089243472364046206735485101139720624790643678231987492090026827166997
Line 727, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log
UVM_FATAL @ 82278461528 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x27ae5b54) == 0x0
UVM_INFO @ 82278461528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
33.spi_host_stress_all.87165229294086151003404439146970126158615426951242848970502922775348313615979
Line 332, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10103620823 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x33a99514) == 0x0
UVM_INFO @ 10103620823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
37.spi_host_status_stall.80899261790074724855512760404717844449330638609986434488724280467334099544077
Line 1118, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_status_stall/latest/run.log
UVM_FATAL @ 178683930395 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x383751d4) == 0x0
UVM_INFO @ 178683930395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 3 failures:
Test spi_host_smoke has 1 failures.
20.spi_host_smoke.105990752313163754267907597449933348126665601895051941588177076762814304177704
Line 937, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_smoke/latest/run.log
UVM_FATAL @ 169945155729 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x360a43d4) == 0x0
UVM_INFO @ 169945155729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
30.spi_host_status_stall.5657686309993939025120889904615180564010331896384788649182938450396151879755
Line 1184, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_status_stall/latest/run.log
UVM_FATAL @ 88535425443 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x987bda94) == 0x0
UVM_INFO @ 88535425443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
49.spi_host_stress_all.31469649909530024732692827145725131767226853820956371720716864640911638442764
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_stress_all/latest/run.log
UVM_FATAL @ 21541894743 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4b189394) == 0x0
UVM_INFO @ 21541894743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == *
has 1 failures:
12.spi_host_status_stall.84775496586088896593643576102540381740298184211163799608275708756564847755417
Line 1118, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log
UVM_FATAL @ 48820871521 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa97d2654) == 0x0
UVM_INFO @ 48820871521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---