abd7ce57f2
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_host_smoke | 11.400m | 85.322ms | 49 | 50 | 98.00 |
V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 17.125us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_host_csr_rw | 3.000s | 19.226us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_host_csr_bit_bash | 4.000s | 353.539us | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 175.035us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 56.972us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 19.226us | 20 | 20 | 100.00 |
spi_host_csr_aliasing | 3.000s | 175.035us | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_host_mem_walk | 2.000s | 14.067us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 32.676us | 5 | 5 | 100.00 |
V1 | TOTAL | 114 | 115 | 99.13 | |||
V2 | performance | spi_host_performance | 3.000s | 30.791us | 50 | 50 | 100.00 |
V2 | error_event_intr | spi_host_overflow_underflow | 3.383m | 15.804ms | 50 | 50 | 100.00 |
spi_host_error_cmd | 3.000s | 29.547us | 50 | 50 | 100.00 | ||
spi_host_event | 19.350m | 27.418ms | 50 | 50 | 100.00 | ||
V2 | clock_rate | spi_host_speed | 5.900m | 7.550ms | 50 | 50 | 100.00 |
V2 | speed | spi_host_speed | 5.900m | 7.550ms | 50 | 50 | 100.00 |
V2 | chip_select_timing | spi_host_speed | 5.900m | 7.550ms | 50 | 50 | 100.00 |
V2 | sw_reset | spi_host_sw_reset | 4.683m | 19.820ms | 50 | 50 | 100.00 |
V2 | passthrough_mode | spi_host_passthrough_mode | 3.000s | 237.491us | 50 | 50 | 100.00 |
V2 | cpol_cpha | spi_host_speed | 5.900m | 7.550ms | 50 | 50 | 100.00 |
V2 | full_cycle | spi_host_speed | 5.900m | 7.550ms | 50 | 50 | 100.00 |
V2 | duplex | spi_host_smoke | 11.400m | 85.322ms | 49 | 50 | 98.00 |
V2 | tx_rx_only | spi_host_smoke | 11.400m | 85.322ms | 49 | 50 | 98.00 |
V2 | stress_all | spi_host_stress_all | 5.200m | 17.396ms | 47 | 50 | 94.00 |
V2 | spien | spi_host_spien | 5.167m | 48.058ms | 49 | 50 | 98.00 |
V2 | stall | spi_host_status_stall | 10.350m | 55.850ms | 50 | 50 | 100.00 |
V2 | Idlecsbactive | spi_host_idlecsbactive | 49.000s | 12.831ms | 50 | 50 | 100.00 |
V2 | data_fifo_status | spi_host_overflow_underflow | 3.383m | 15.804ms | 50 | 50 | 100.00 |
V2 | alert_test | spi_host_alert_test | 3.000s | 26.609us | 50 | 50 | 100.00 |
V2 | intr_test | spi_host_intr_test | 3.000s | 138.157us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 445.708us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 445.708us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 17.125us | 5 | 5 | 100.00 |
spi_host_csr_rw | 3.000s | 19.226us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 3.000s | 175.035us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 3.000s | 32.358us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 17.125us | 5 | 5 | 100.00 |
spi_host_csr_rw | 3.000s | 19.226us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 3.000s | 175.035us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 3.000s | 32.358us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 686 | 690 | 99.42 | |||
V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 95.964us | 20 | 20 | 100.00 |
spi_host_sec_cm | 3.000s | 186.325us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 95.964us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | winbond | winbond | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 825 | 830 | 99.40 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 7 | 87.50 |
V2 | 15 | 15 | 13 | 86.67 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 2 | 0 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
91.00 | 90.92 | 83.18 | 92.77 | 89.69 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == *
has 2 failures:
3.spi_host_stress_all.94533907652181714528967188666672101590534083898375558000863063261432331913176
Line 412, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_stress_all/latest/run.log
UVM_FATAL @ 17396049341 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc4c07994) == 0x0
UVM_INFO @ 17396049341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.spi_host_stress_all.73856958601617377648896403266665612506056332509320516920185404905650355401828
Line 386, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10005773807 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe7e25414) == 0x0
UVM_INFO @ 10005773807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 2 failures:
Test spi_host_stress_all has 1 failures.
5.spi_host_stress_all.100071193896788984498163824850806455672245815237639843755358559214337445784018
Line 409, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/latest/run.log
UVM_FATAL @ 17337249028 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcafd9bd4) == 0x0
UVM_INFO @ 17337249028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
25.spi_host_smoke.112486146217578002368866276692251790021029539549723957708356818693301617215209
Line 935, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_smoke/latest/run.log
UVM_FATAL @ 164062863047 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xaebab94) == 0x0
UVM_INFO @ 164062863047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1259) [UVM/FLD/SET/BSY] Setting the value of field "tx_watermark" while containing register "spi_host_reg_block.control" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
has 1 failures:
2.spi_host_spien.101521653375122471165216914769381139950228561429988180160141412197299696779711
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_spien/latest/run.log
UVM_WARNING @ 1336209 ps: (uvm_reg_field.svh:1259) [UVM/FLD/SET/BSY] Setting the value of field "tx_watermark" while containing register "spi_host_reg_block.control" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 1336209 ps: (uvm_reg_field.svh:1259) [UVM/FLD/SET/BSY] Setting the value of field "rx_watermark" while containing register "spi_host_reg_block.control" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 1336209 ps: (uvm_reg_field.svh:1259) [UVM/FLD/SET/BSY] Setting the value of field "spien" while containing register "spi_host_reg_block.control" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 1336209 ps: (uvm_reg_field.svh:1259) [UVM/FLD/SET/BSY] Setting the value of field "output_en" while containing register "spi_host_reg_block.control" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_INFO @ 1751091 ps: (spi_host_base_vseq.sv:344) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_host_spien_vseq]