e6706fcc7b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 8.950m | 21.543ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 21.272us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 7.000s | 25.186us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 8.000s | 35.317us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 308.221us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 18.000s | 28.946us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 7.000s | 25.186us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 308.221us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 16.886us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 141.735us | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | performance | spi_host_performance | 4.000s | 32.930us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.233m | 38.515ms | 48 | 50 | 96.00 |
| spi_host_error_cmd | 3.000s | 34.923us | 50 | 50 | 100.00 | ||
| spi_host_event | 22.667m | 35.679ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 5.850m | 25.942ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 5.850m | 25.942ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 5.850m | 25.942ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 4.400m | 15.558ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 3.000s | 354.836us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 5.850m | 25.942ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 5.850m | 25.942ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 8.950m | 21.543ms | 49 | 50 | 98.00 |
| V2 | tx_rx_only | spi_host_smoke | 8.950m | 21.543ms | 49 | 50 | 98.00 |
| V2 | stress_all | spi_host_stress_all | 3.850m | 12.365ms | 46 | 50 | 92.00 |
| V2 | spien | spi_host_spien | 6.850m | 14.927ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 8.717m | 12.178ms | 49 | 50 | 98.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 47.000s | 7.262ms | 50 | 50 | 100.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 3.233m | 38.515ms | 48 | 50 | 96.00 |
| V2 | alert_test | spi_host_alert_test | 3.000s | 16.554us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 7.000s | 54.430us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 9.000s | 119.534us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 9.000s | 119.534us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 21.272us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 25.186us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 308.221us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 7.000s | 36.225us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 21.272us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 25.186us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 308.221us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 7.000s | 36.225us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 683 | 690 | 98.99 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 8.000s | 326.044us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 2.000s | 132.643us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 8.000s | 326.044us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 822 | 830 | 99.04 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 12 | 80.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 90.99 | 90.92 | 83.18 | 92.77 | 89.61 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 7 failures:
Test spi_host_overflow_underflow has 2 failures.
9.spi_host_overflow_underflow.91851962069954542565120414188689201372582511200135608423271475482404312334496
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 38515399636 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa125ff14) == 0x0
UVM_INFO @ 38515399636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.spi_host_overflow_underflow.29537097537498945243366389540314161205541039598771778928330744325994070294795
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 50708637694 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd5cc5ad4) == 0x0
UVM_INFO @ 50708637694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 4 failures.
32.spi_host_stress_all.11881686481666585558319488444195989066341911498990258126131953873637197224537
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_stress_all/latest/run.log
UVM_FATAL @ 13340184346 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3aa9b254) == 0x0
UVM_INFO @ 13340184346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.spi_host_stress_all.78368817232476698603223784123872008704724025407327239516017390601260654754294
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_stress_all/latest/run.log
UVM_FATAL @ 21377916672 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x87825ad4) == 0x0
UVM_INFO @ 21377916672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_smoke has 1 failures.
38.spi_host_smoke.89274542009081270743728135426884228090872380103040562579456817767653294043594
Line 863, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_smoke/latest/run.log
UVM_FATAL @ 162885148989 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x119b32d4) == 0x0
UVM_INFO @ 162885148989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
2.spi_host_status_stall.112891787917902000660767078879533026627124702689515673752013157444840381879575
Line 1238, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
UVM_FATAL @ 93082319921 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x84837154) == 0x0
UVM_INFO @ 93082319921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---