3e678c112b
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_host_smoke | 6.383m | 8.781ms | 24 | 50 | 48.00 |
V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 81.770us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_host_csr_rw | 4.000s | 36.338us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_host_csr_bit_bash | 6.000s | 461.794us | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_host_csr_aliasing | 4.000s | 133.687us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 5.000s | 27.563us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 4.000s | 36.338us | 20 | 20 | 100.00 |
spi_host_csr_aliasing | 4.000s | 133.687us | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_host_mem_walk | 3.000s | 15.924us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 38.818us | 5 | 5 | 100.00 |
V1 | TOTAL | 89 | 115 | 77.39 | |||
V2 | performance | spi_host_performance | 4.000s | 274.603us | 50 | 50 | 100.00 |
V2 | error_event_intr | spi_host_overflow_underflow | 2.717m | 15.201ms | 50 | 50 | 100.00 |
spi_host_error_cmd | 3.000s | 17.720us | 50 | 50 | 100.00 | ||
spi_host_event | 14.733m | 89.686ms | 50 | 50 | 100.00 | ||
V2 | clock_rate | spi_host_speed | 18.000s | 9.891ms | 23 | 50 | 46.00 |
V2 | speed | spi_host_speed | 18.000s | 9.891ms | 23 | 50 | 46.00 |
V2 | chip_select_timing | spi_host_speed | 18.000s | 9.891ms | 23 | 50 | 46.00 |
V2 | sw_reset | spi_host_sw_reset | 2.683m | 5.090ms | 26 | 50 | 52.00 |
V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 908.405us | 50 | 50 | 100.00 |
V2 | cpol_cpha | spi_host_speed | 18.000s | 9.891ms | 23 | 50 | 46.00 |
V2 | full_cycle | spi_host_speed | 18.000s | 9.891ms | 23 | 50 | 46.00 |
V2 | duplex | spi_host_smoke | 6.383m | 8.781ms | 24 | 50 | 48.00 |
V2 | tx_rx_only | spi_host_smoke | 6.383m | 8.781ms | 24 | 50 | 48.00 |
V2 | stress_all | spi_host_stress_all | 1.983m | 2.353ms | 31 | 50 | 62.00 |
V2 | spien | spi_host_spien | 7.167m | 9.054ms | 22 | 50 | 44.00 |
V2 | stall | spi_host_status_stall | 2.800m | 11.289ms | 22 | 50 | 44.00 |
V2 | Idlecsbactive | spi_host_idlecsbactive | 44.000s | 1.825ms | 26 | 50 | 52.00 |
V2 | data_fifo_status | spi_host_overflow_underflow | 2.717m | 15.201ms | 50 | 50 | 100.00 |
V2 | alert_test | spi_host_alert_test | 3.000s | 16.061us | 50 | 50 | 100.00 |
V2 | intr_test | spi_host_intr_test | 3.000s | 34.995us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_host_tl_errors | 6.000s | 92.068us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_host_tl_errors | 6.000s | 92.068us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 81.770us | 5 | 5 | 100.00 |
spi_host_csr_rw | 4.000s | 36.338us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 4.000s | 133.687us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 4.000s | 153.120us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 81.770us | 5 | 5 | 100.00 |
spi_host_csr_rw | 4.000s | 36.338us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 4.000s | 133.687us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 4.000s | 153.120us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 540 | 690 | 78.26 | |||
V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 88.791us | 20 | 20 | 100.00 |
spi_host_sec_cm | 3.000s | 62.073us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 88.791us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | winbond | winbond | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
Unmapped tests | spi_host_upper_range_clkdiv | 51.033m | 200.000ms | 1 | 10 | 10.00 | |
TOTAL | 655 | 840 | 77.98 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
N.A. | 1 | 1 | 0 | 0.00 |
V1 | 8 | 8 | 7 | 87.50 |
V2 | 15 | 15 | 9 | 60.00 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 2 | 0 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
91.00 | 90.92 | 83.18 | 92.77 | 89.69 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
has 177 failures:
0.spi_host_smoke.39115175730839525421164710454069239845550954634921359564116929331496663984049
Line 324, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log
UVM_FATAL @ 6514980 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 6514980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_smoke.101823478321872956919991628815585018249834276631509324252498313182676801410302
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log
UVM_FATAL @ 969646 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 969646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
0.spi_host_speed.44364424337090259755774943562856522177205487131044555905969136737387959001026
Line 310, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_speed/latest/run.log
UVM_FATAL @ 3861450 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 3861450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_speed.94140052085055797506305188288364094220860365614924518320816564542441272054352
Line 310, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_speed/latest/run.log
UVM_FATAL @ 4558601 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 4558601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
0.spi_host_sw_reset.94161415350405978550106147868024689975754473083730532327115479287035020362638
Line 297, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 1719388 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 1719388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_sw_reset.112070234317791877570850847105307726182361770398179272375158223463549971163190
Line 297, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 1994419 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 1994419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
1.spi_host_status_stall.15715037188522000800194382562383780247628593222606992871274770136301214960217
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 20357220 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 20357220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_status_stall.6023754300764936845243773721717667164342868424814321798142776418099645632035
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
UVM_FATAL @ 8276415 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 8276415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
1.spi_host_spien.71481077833192656642933442659602717215506284208308076949681461306963176443432
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_spien/latest/run.log
UVM_FATAL @ 4143338 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 4143338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_spien.105039707506230499237133401407556698236511289313987521433548958894602706569108
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_spien/latest/run.log
UVM_FATAL @ 1728003 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 1728003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 2 failures:
6.spi_host_upper_range_clkdiv.79552770824441463125133073938969465760659899177431436316693052223647324408552
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:44e08038-619d-4021-a26c-c7ee7454fa89
9.spi_host_upper_range_clkdiv.92629227757475848595617922655063032929504111962072771725129673203193429301058
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:dea34071-4130-4e4d-b798-afd1691473bb
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == *
has 2 failures:
23.spi_host_status_stall.90325908978261199264980370018876986878026240872023812582462958643499970551862
Line 941, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10534783292 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xbdd44b94) == 0x1
UVM_INFO @ 10534783292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_host_status_stall.107019162523621649869759189596161850830774098823591845885039246969769443174900
Line 909, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10039194103 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xcec26b14) == 0x1
UVM_INFO @ 10039194103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == *
has 1 failures:
0.spi_host_upper_range_clkdiv.103881783706099241969719063130689178032532268720617697990023630926040501383912
Line 315, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002550311 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf65d3a14) == 0x0
UVM_INFO @ 100002550311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 1 failures:
8.spi_host_upper_range_clkdiv.78111530984906586757060782939648175857514975237354253239963204583044760363851
Line 383, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 1 failures:
33.spi_host_smoke.77538370133262859635558604378379196037708071150618562401757440803219948954865
Line 889, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_smoke/latest/run.log
UVM_FATAL @ 110533844950 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa327b694) == 0x0
UVM_INFO @ 110533844950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == *
has 1 failures:
41.spi_host_status_stall.70831383949298535140490530331919305605637839402490755583305346292681702418974
Line 983, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10257716238 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xadd11f94) == 0x1
UVM_INFO @ 10257716238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---