SPI_HOST Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 6.383m 8.781ms 24 50 48.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 81.770us 5 5 100.00
V1 csr_rw spi_host_csr_rw 4.000s 36.338us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 6.000s 461.794us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 4.000s 133.687us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 5.000s 27.563us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 4.000s 36.338us 20 20 100.00
spi_host_csr_aliasing 4.000s 133.687us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 15.924us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 38.818us 5 5 100.00
V1 TOTAL 89 115 77.39
V2 performance spi_host_performance 4.000s 274.603us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.717m 15.201ms 50 50 100.00
spi_host_error_cmd 3.000s 17.720us 50 50 100.00
spi_host_event 14.733m 89.686ms 50 50 100.00
V2 clock_rate spi_host_speed 18.000s 9.891ms 23 50 46.00
V2 speed spi_host_speed 18.000s 9.891ms 23 50 46.00
V2 chip_select_timing spi_host_speed 18.000s 9.891ms 23 50 46.00
V2 sw_reset spi_host_sw_reset 2.683m 5.090ms 26 50 52.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 908.405us 50 50 100.00
V2 cpol_cpha spi_host_speed 18.000s 9.891ms 23 50 46.00
V2 full_cycle spi_host_speed 18.000s 9.891ms 23 50 46.00
V2 duplex spi_host_smoke 6.383m 8.781ms 24 50 48.00
V2 tx_rx_only spi_host_smoke 6.383m 8.781ms 24 50 48.00
V2 stress_all spi_host_stress_all 1.983m 2.353ms 31 50 62.00
V2 spien spi_host_spien 7.167m 9.054ms 22 50 44.00
V2 stall spi_host_status_stall 2.800m 11.289ms 22 50 44.00
V2 Idlecsbactive spi_host_idlecsbactive 44.000s 1.825ms 26 50 52.00
V2 data_fifo_status spi_host_overflow_underflow 2.717m 15.201ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 16.061us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 34.995us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 6.000s 92.068us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 6.000s 92.068us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 81.770us 5 5 100.00
spi_host_csr_rw 4.000s 36.338us 20 20 100.00
spi_host_csr_aliasing 4.000s 133.687us 5 5 100.00
spi_host_same_csr_outstanding 4.000s 153.120us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 81.770us 5 5 100.00
spi_host_csr_rw 4.000s 36.338us 20 20 100.00
spi_host_csr_aliasing 4.000s 133.687us 5 5 100.00
spi_host_same_csr_outstanding 4.000s 153.120us 20 20 100.00
V2 TOTAL 540 690 78.26
V2S tl_intg_err spi_host_tl_intg_err 4.000s 88.791us 20 20 100.00
spi_host_sec_cm 3.000s 62.073us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 88.791us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 51.033m 200.000ms 1 10 10.00
TOTAL 655 840 77.98

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.00 90.92 83.18 92.77 89.69 95.70 100.00 95.07 90.87

Failure Buckets

Past Results