9edf84e236| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 6.950m | 10.587ms | 20 | 50 | 40.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 57.861us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 29.863us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 138.480us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 22.905us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 7.000s | 127.561us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 29.863us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 22.905us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 42.687us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 5.000s | 46.055us | 5 | 5 | 100.00 |
| V1 | TOTAL | 85 | 115 | 73.91 | |||
| V2 | performance | spi_host_performance | 13.000s | 30.029us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.917m | 8.290ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 8.000s | 52.297us | 50 | 50 | 100.00 | ||
| spi_host_event | 24.750m | 192.154ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 30.000s | 8.014ms | 28 | 50 | 56.00 |
| V2 | speed | spi_host_speed | 30.000s | 8.014ms | 28 | 50 | 56.00 |
| V2 | chip_select_timing | spi_host_speed | 30.000s | 8.014ms | 28 | 50 | 56.00 |
| V2 | sw_reset | spi_host_sw_reset | 1.567m | 3.378ms | 20 | 50 | 40.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 17.000s | 288.826us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 30.000s | 8.014ms | 28 | 50 | 56.00 |
| V2 | full_cycle | spi_host_speed | 30.000s | 8.014ms | 28 | 50 | 56.00 |
| V2 | duplex | spi_host_smoke | 6.950m | 10.587ms | 20 | 50 | 40.00 |
| V2 | tx_rx_only | spi_host_smoke | 6.950m | 10.587ms | 20 | 50 | 40.00 |
| V2 | stress_all | spi_host_stress_all | 3.217m | 10.059ms | 18 | 50 | 36.00 |
| V2 | spien | spi_host_spien | 46.000s | 4.477ms | 24 | 50 | 48.00 |
| V2 | stall | spi_host_status_stall | 9.167m | 53.883ms | 23 | 50 | 46.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 11.000s | 2.012us | 23 | 50 | 46.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 2.917m | 8.290ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 7.000s | 52.846us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 4.000s | 16.373us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 9.000s | 72.355us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 9.000s | 72.355us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 57.861us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 29.863us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 22.905us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 35.319us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 57.861us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 29.863us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 22.905us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 35.319us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 526 | 690 | 76.23 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 8.000s | 49.561us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 68.391us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 8.000s | 49.561us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 51.817m | 100.004ms | 0 | 10 | 0.00 | |
| TOTAL | 636 | 840 | 75.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.77 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed! has 196 failures:
0.spi_host_speed.70442350352312238075198828739223415838826274558502194929837823047769432013488
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_speed/latest/run.log
UVM_FATAL @ 9935998 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 9935998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_speed.66874539420278797424477158104517587066332310482621365860329651356612271209980
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_speed/latest/run.log
UVM_FATAL @ 3617642 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 3617642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
0.spi_host_sw_reset.64224831327641774148910482905368351435283380118036467803155048738800196153742
Line 297, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 7411381 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 7411381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_sw_reset.40970203232298369762301514494875212394513489665366071375772734007426964964840
Line 297, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 1155613 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 1155613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
0.spi_host_idlecsbactive.73184490619778200108891946583878099246765378421218379369748532855447398716800
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 3218474 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 3218474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_idlecsbactive.17111231605104064358956731182274056421520627708395641114072435180151814504676
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 1303524 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 1303524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
0.spi_host_stress_all.71857630460280031776102218900194690551868428927858473654311296973142159253143
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_stress_all/latest/run.log
UVM_FATAL @ 14746756 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 14746756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_stress_all.95011382019764524396555842218203010939811593027359911700505986266953880846473
Line 297, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_stress_all/latest/run.log
UVM_FATAL @ 1989576 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 1989576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
1.spi_host_smoke.103431243148852388520006115600934408059183397298926872094269351808003140490050
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log
UVM_FATAL @ 5193251 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 5193251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_smoke.54870327878729708463055876894307194420083755925345382768466090585498353380567
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_smoke/latest/run.log
UVM_FATAL @ 5724219 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 5724219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 6 failures:
1.spi_host_upper_range_clkdiv.48587175826595606022495403419498890307345352407569538517429314280954740844550
Line 311, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002807526 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa5f30e94) == 0x0
UVM_INFO @ 100002807526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_upper_range_clkdiv.71665909710637103462022776373886288768261755011720795877025484833796066361029
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100004491815 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9a02a494) == 0x0
UVM_INFO @ 100004491815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
29.spi_host_stress_all.65648578723731830124768922152643177643659323779520925761511885722675690893788
Line 419, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10058782118 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3f9d2254) == 0x0
UVM_INFO @ 10058782118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
0.spi_host_upper_range_clkdiv.95336784116328530874934613129195077740994368058899837843843446833969109132554
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100005792218 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x44c7fd14) == 0x0
UVM_INFO @ 100005792218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
21.spi_host_status_stall.39465344102879775877163095875405406024278718774179497452738514895300191897774
Line 977, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10456018383 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe6391714) == 0x1
UVM_INFO @ 10456018383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---