SPI_HOST Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 6.767m 8.662ms 23 50 46.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 34.110us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 51.777us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 4.000s 57.170us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 2.000s 109.642us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 25.067us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 51.777us 20 20 100.00
spi_host_csr_aliasing 2.000s 109.642us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 14.316us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 24.246us 5 5 100.00
V1 TOTAL 88 115 76.52
V2 performance spi_host_performance 4.000s 32.478us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.633m 7.052ms 50 50 100.00
spi_host_error_cmd 3.000s 59.623us 50 50 100.00
spi_host_event 21.400m 65.254ms 50 50 100.00
V2 clock_rate spi_host_speed 29.000s 570.301us 27 50 54.00
V2 speed spi_host_speed 29.000s 570.301us 27 50 54.00
V2 chip_select_timing spi_host_speed 29.000s 570.301us 27 50 54.00
V2 sw_reset spi_host_sw_reset 13.083m 45.431ms 31 50 62.00
V2 passthrough_mode spi_host_passthrough_mode 3.000s 309.015us 50 50 100.00
V2 cpol_cpha spi_host_speed 29.000s 570.301us 27 50 54.00
V2 full_cycle spi_host_speed 29.000s 570.301us 27 50 54.00
V2 duplex spi_host_smoke 6.767m 8.662ms 23 50 46.00
V2 tx_rx_only spi_host_smoke 6.767m 8.662ms 23 50 46.00
V2 stress_all spi_host_stress_all 1.667m 5.746ms 24 50 48.00
V2 spien spi_host_spien 1.100m 13.510ms 25 50 50.00
V2 stall spi_host_status_stall 7.583m 10.155ms 29 50 58.00
V2 Idlecsbactive spi_host_idlecsbactive 42.000s 1.489ms 30 50 60.00
V2 data_fifo_status spi_host_overflow_underflow 2.633m 7.052ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 14.303us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 27.095us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 4.000s 68.610us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 4.000s 68.610us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 34.110us 5 5 100.00
spi_host_csr_rw 3.000s 51.777us 20 20 100.00
spi_host_csr_aliasing 2.000s 109.642us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 126.832us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 34.110us 5 5 100.00
spi_host_csr_rw 3.000s 51.777us 20 20 100.00
spi_host_csr_aliasing 2.000s 109.642us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 126.832us 20 20 100.00
V2 TOTAL 556 690 80.58
V2S tl_intg_err spi_host_tl_intg_err 3.000s 268.773us 20 20 100.00
spi_host_sec_cm 3.000s 490.115us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 3.000s 268.773us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 58.567m 100.003ms 3 10 30.00
TOTAL 672 840 80.00

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
90.98 90.92 83.18 92.77 89.53 95.70 100.00 95.07 90.87

Failure Buckets

Past Results