2e5d86c9b5
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_host_smoke | 6.433m | 35.313ms | 24 | 50 | 48.00 |
V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 24.887us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_host_csr_rw | 18.000s | 65.295us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_host_csr_bit_bash | 19.000s | 238.824us | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_host_csr_aliasing | 12.000s | 52.646us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 8.000s | 81.153us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 18.000s | 65.295us | 20 | 20 | 100.00 |
spi_host_csr_aliasing | 12.000s | 52.646us | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_host_mem_walk | 2.000s | 34.102us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_host_mem_partial_access | 7.000s | 15.074us | 5 | 5 | 100.00 |
V1 | TOTAL | 89 | 115 | 77.39 | |||
V2 | performance | spi_host_performance | 8.000s | 33.035us | 50 | 50 | 100.00 |
V2 | error_event_intr | spi_host_overflow_underflow | 3.250m | 15.743ms | 50 | 50 | 100.00 |
spi_host_error_cmd | 7.000s | 15.707us | 50 | 50 | 100.00 | ||
spi_host_event | 8.933m | 43.745ms | 50 | 50 | 100.00 | ||
V2 | clock_rate | spi_host_speed | 15.000s | 265.583us | 25 | 50 | 50.00 |
V2 | speed | spi_host_speed | 15.000s | 265.583us | 25 | 50 | 50.00 |
V2 | chip_select_timing | spi_host_speed | 15.000s | 265.583us | 25 | 50 | 50.00 |
V2 | sw_reset | spi_host_sw_reset | 1.983m | 6.658ms | 34 | 50 | 68.00 |
V2 | passthrough_mode | spi_host_passthrough_mode | 18.000s | 512.398us | 50 | 50 | 100.00 |
V2 | cpol_cpha | spi_host_speed | 15.000s | 265.583us | 25 | 50 | 50.00 |
V2 | full_cycle | spi_host_speed | 15.000s | 265.583us | 25 | 50 | 50.00 |
V2 | duplex | spi_host_smoke | 6.433m | 35.313ms | 24 | 50 | 48.00 |
V2 | tx_rx_only | spi_host_smoke | 6.433m | 35.313ms | 24 | 50 | 48.00 |
V2 | stress_all | spi_host_stress_all | 1.500m | 2.022ms | 26 | 50 | 52.00 |
V2 | spien | spi_host_spien | 7.150m | 33.148ms | 27 | 50 | 54.00 |
V2 | stall | spi_host_status_stall | 3.067m | 107.277ms | 23 | 50 | 46.00 |
V2 | Idlecsbactive | spi_host_idlecsbactive | 1.133m | 26.723ms | 24 | 50 | 48.00 |
V2 | data_fifo_status | spi_host_overflow_underflow | 3.250m | 15.743ms | 50 | 50 | 100.00 |
V2 | alert_test | spi_host_alert_test | 9.000s | 30.459us | 50 | 50 | 100.00 |
V2 | intr_test | spi_host_intr_test | 12.000s | 57.083us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_host_tl_errors | 10.000s | 309.427us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_host_tl_errors | 10.000s | 309.427us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 24.887us | 5 | 5 | 100.00 |
spi_host_csr_rw | 18.000s | 65.295us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 12.000s | 52.646us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 8.000s | 101.795us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 24.887us | 5 | 5 | 100.00 |
spi_host_csr_rw | 18.000s | 65.295us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 12.000s | 52.646us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 8.000s | 101.795us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 549 | 690 | 79.57 | |||
V2S | tl_intg_err | spi_host_tl_intg_err | 12.000s | 666.708us | 20 | 20 | 100.00 |
spi_host_sec_cm | 3.000s | 565.313us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 12.000s | 666.708us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | winbond | winbond | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
Unmapped tests | spi_host_upper_range_clkdiv | 52.133m | 100.004ms | 0 | 10 | 0.00 | |
TOTAL | 663 | 840 | 78.93 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
N.A. | 1 | 1 | 0 | 0.00 |
V1 | 8 | 8 | 7 | 87.50 |
V2 | 15 | 15 | 9 | 60.00 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 2 | 0 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
91.00 | 90.92 | 83.18 | 92.77 | 89.69 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
has 170 failures:
0.spi_host_smoke.6543924289370644207166094333848866184451869672193557796777925986204226036835
Line 324, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log
UVM_FATAL @ 15685944 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 15685944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_smoke.74053745587155794277679833368596496337684629932817697420047044226958414689140
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log
UVM_FATAL @ 4291474 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 4291474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
0.spi_host_upper_range_clkdiv.89670723456448583953503442506513129765561253365589012881507881852838284248468
Line 310, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 8751527 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 8751527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_upper_range_clkdiv.39394111990903018615541332012668480871125469262208305236666622654274712093569
Line 310, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 1319327 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 1319327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
0.spi_host_sw_reset.74029588398393465546846326517835840293961009553440395055717962044114727330008
Line 332, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 434690587 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 434690587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_sw_reset.85616289134159406219511294293810929760251899837529206957563779986116546131993
Line 297, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 5991008 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 5991008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
0.spi_host_idlecsbactive.38474789505090297838864175312137719900319967881602663839905146876080181117759
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 26275525 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 26275525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_idlecsbactive.53827320208145642078888441778704927849606165774700882781915786809838558209656
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 4889385 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 4889385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
1.spi_host_stress_all.79940379104880936099100742186097866171465103160151167860026215759080558810809
Line 310, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_stress_all/latest/run.log
UVM_FATAL @ 3612229 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 3612229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_stress_all.70686035507250395053543211159645557833495852235649254402361126744645367478919
Line 296, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_stress_all/latest/run.log
UVM_FATAL @ 1018632 ps: (spi_transaction_item.sv:134) [transaction] Check failed (segment.randomize()) Randomization failed!
UVM_INFO @ 1018632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == *
has 4 failures:
2.spi_host_upper_range_clkdiv.16806604819789530175184768135325749597996603330320705429137743293763475838234
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100000821904 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x18559b94) == 0x0
UVM_INFO @ 100000821904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_upper_range_clkdiv.63017198868360396634839965813453472336339959806010401965740493079473192832820
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003539401 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x83bf0a54) == 0x0
UVM_INFO @ 100003539401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == *
has 1 failures:
2.spi_host_status_stall.43232965517304882585768993675212307034478084865628449926994966245865984183029
Line 977, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
UVM_FATAL @ 17151388286 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x692e3c94) == 0x1
UVM_INFO @ 17151388286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == *
has 1 failures:
4.spi_host_upper_range_clkdiv.82938109655827368914447083598859093394991398380969615926961557489743047903189
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100010447266 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5e23e0d4) == 0x0
UVM_INFO @ 100010447266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 1 failures:
7.spi_host_upper_range_clkdiv.30217483855819582428340803167496578723039604149363030753854414462101359956639
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:a40a1df8-c482-44fb-8eb5-17985f1e369d