SPI_HOST Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 6.433m 35.313ms 24 50 48.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 24.887us 5 5 100.00
V1 csr_rw spi_host_csr_rw 18.000s 65.295us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 19.000s 238.824us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 12.000s 52.646us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 8.000s 81.153us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 18.000s 65.295us 20 20 100.00
spi_host_csr_aliasing 12.000s 52.646us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 34.102us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 7.000s 15.074us 5 5 100.00
V1 TOTAL 89 115 77.39
V2 performance spi_host_performance 8.000s 33.035us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.250m 15.743ms 50 50 100.00
spi_host_error_cmd 7.000s 15.707us 50 50 100.00
spi_host_event 8.933m 43.745ms 50 50 100.00
V2 clock_rate spi_host_speed 15.000s 265.583us 25 50 50.00
V2 speed spi_host_speed 15.000s 265.583us 25 50 50.00
V2 chip_select_timing spi_host_speed 15.000s 265.583us 25 50 50.00
V2 sw_reset spi_host_sw_reset 1.983m 6.658ms 34 50 68.00
V2 passthrough_mode spi_host_passthrough_mode 18.000s 512.398us 50 50 100.00
V2 cpol_cpha spi_host_speed 15.000s 265.583us 25 50 50.00
V2 full_cycle spi_host_speed 15.000s 265.583us 25 50 50.00
V2 duplex spi_host_smoke 6.433m 35.313ms 24 50 48.00
V2 tx_rx_only spi_host_smoke 6.433m 35.313ms 24 50 48.00
V2 stress_all spi_host_stress_all 1.500m 2.022ms 26 50 52.00
V2 spien spi_host_spien 7.150m 33.148ms 27 50 54.00
V2 stall spi_host_status_stall 3.067m 107.277ms 23 50 46.00
V2 Idlecsbactive spi_host_idlecsbactive 1.133m 26.723ms 24 50 48.00
V2 data_fifo_status spi_host_overflow_underflow 3.250m 15.743ms 50 50 100.00
V2 alert_test spi_host_alert_test 9.000s 30.459us 50 50 100.00
V2 intr_test spi_host_intr_test 12.000s 57.083us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 10.000s 309.427us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 10.000s 309.427us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 24.887us 5 5 100.00
spi_host_csr_rw 18.000s 65.295us 20 20 100.00
spi_host_csr_aliasing 12.000s 52.646us 5 5 100.00
spi_host_same_csr_outstanding 8.000s 101.795us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 24.887us 5 5 100.00
spi_host_csr_rw 18.000s 65.295us 20 20 100.00
spi_host_csr_aliasing 12.000s 52.646us 5 5 100.00
spi_host_same_csr_outstanding 8.000s 101.795us 20 20 100.00
V2 TOTAL 549 690 79.57
V2S tl_intg_err spi_host_tl_intg_err 12.000s 666.708us 20 20 100.00
spi_host_sec_cm 3.000s 565.313us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 12.000s 666.708us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 52.133m 100.004ms 0 10 0.00
TOTAL 663 840 78.93

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.00 90.92 83.18 92.77 89.69 95.70 100.00 95.07 90.87

Failure Buckets

Past Results